SNAS722B december 2017 – august 2023 LMK61E07
PRODUCTION DATA
The PLL_FRACDEN_BY1 register is described in the following table.
BIT NO. | FIELD | TYPE | DEFAULT | EEPROM | DESCRIPTION |
---|---|---|---|---|---|
[7:0] | PLL_DEN[15:8] | RW | 0x02 | Y | PLL Fractional Divider Denominator Byte 1. Bits
[15:8]. |