SNAS722B december 2017 – august 2023 LMK61E07
PRODUCTION DATA
The SWRST1 register provides software reset control for specific on-chip modules. Each bit in this register is individually self cleared after a write operation. The SWRST1 register will always return 0x00 in a read transaction.
BIT NO. | FIELD | TYPE | DEFAULT | EEPROM | DESCRIPTION |
---|---|---|---|---|---|
[7:2] | RESERVED | - | - | N |
Reserved. |
[1] | SWR2PLL | RWSC | 0 | N |
Software Reset PLL.
Setting SWR2PLL to 1 resets the PLL calibrator and clock dividers. This bit is automatically cleared to 0. |
[0] | RESERVED | - | - | N |
Reserved. |