SNAS722B december 2017 – august 2023 LMK61E07
PRODUCTION DATA
The MEMADR register holds 7-bits of the starting address for on-chip SRAM or EEPROM access.
BIT NO. | FIELD | TYPE | DEFAULT | EEPROM | DESCRIPTION |
---|---|---|---|---|---|
[7] | RESERVED | - | - | N |
Reserved. |
[6:0] | MEMADR[6:0] | RW | 0x00 | N |
Memory Address.
The MEMADR value determines the starting address for on-chip SRAM read/write access or on-chip EEPROM access. The internal address to access SRAM or EEPROM is automatically incremented; however the MEMADR register does not reflect the internal address in this way. When the SRAM or EEPROM arrays are accessed using the I2C interface only bits [4:0] of MEMADR are used to form the byte Wise address. |