SNAS722B december 2017 – august 2023 LMK61E07
PRODUCTION DATA
The RAMDAT register provides read and write access to the SRAM that forms part of the on-chip EEPROM module.
BIT NO. | FIELD | TYPE | DEFAULT | EEPROM | DESCRIPTION |
---|---|---|---|---|---|
[7:0] | RAMDAT[7:0] | RW | 0x00 | N | RAM Read/Write Data. The first time an I2C read or write
transaction accesses the RAMDAT register address, either because it was explicitly
targeted or because the address was auto-incremented, a read transaction will return
the RAM data located at the address specified by the MEMADR register and a write
transaction will cause the current I2C data to be written to the address
specified by the MEMADR register. Any additional accesses which are part of the same
transaction will cause the RAM address to be incremented and a read or write access
will take place to the next SRAM address. The I2C address will no longer
be auto-incremented, that is the I2C address will be locked to the RAMDAT
register after the first access. Access to the RAMDAT register will terminate at the
end of the current I2C transaction. |