SNAS724A February 2018 – April 2018 LMK05028
PRODUCTION DATA.
Each PLL channel supports programmable loop bandwidth for jitter and wander attenuation and fractional frequency translation for flexible frequency configuration. Synchronization options supported on each PLL channel includes hitless switching with phase cancellation, digital holdover, DCO mode with <1 ppt/step for precise clock steering (IEEE 1588 PTP slave), and zero-delay mode for deterministic input-to-output phase offset. The advanced reference input monitoring block ensures robust clock fault detection and helps to minimize output clock disturbance when a loss of reference (LOR) occurs.
The device can use a low-frequency TCXO/OCXO to determine the free-run or holdover frequency stability to maintain standards-compliant synchronization during LOR, or a standard XO when holdover frequency stability and wander are not critical. The device is fully programmable through I2C or SPI interface and supports custom frequency configuration on power-up with the internal EEPROM or ROM. The EEPROM is factory pre-programmable and in-system programmable.
AC-LVPECL output, fIN = 25 MHz, fTCXO = 10 MHz (OCXO), fXO = 48.0048 MHz, fTCXO-TDC = 20 MHz |