SNAS724A February 2018 – April 2018
PRODUCTION DATA.
When output auto-mute is enabled, any output derived from a PLL will start up in synchronous fashion without clock glitches when PLL lock is achieved after any the following events: device power-on, exiting hard reset (PDN pin), exiting soft reset (RESET_SW bit), or exiting PLL reset (PLLx_PDN bit). The output clock will also start up without glitches after any of the following events: VDDO_x is ramped (even when delayed after the device initialization), exiting channel soft reset (CHxPWDN bit), or deassertion of output SYNC (assuming SYNC_MUTE bit is set).