LMK05028 Low-Jitter Dual-Channel Network Synchronizer Clock With EEPROM

1 Features

Two Independent PLL Channels Featuring:
- Jitter: 150fs RMS for Outputs ≥ 100MHz
- Phase Noise: –112dBc/Hz at 100Hz Offset for 122.88MHz
- Hitless Switching: 50ps Phase Transient With Phase Cancellation
- Programmable Loop Bandwidth With Fastlock
- Standards-Compliant Synchronization and Holdover Using a Low-Cost TCXO/OCXO
- Any Input to Any Output Frequency Translation
Four Reference Clock Inputs
- Priority-Based Input Selection
- Digital Holdover on Loss of Reference
Eight Clock Outputs With Programmable Drivers
- Up to Six Different Output Frequencies
- AC-LVDS, AC-CML, AC-LVPECL, HCSL, and 1.8V or 2.5V LVCMOS Output Formats
EEPROM/ROM for Custom Clocks on Power-Up
Flexible Configuration Options
- Up to 750MHz on Input and Output
- XO: 10MHz to 100MHz, TCXO: 10MHz to 54MHz
- DCO Mode: < 1ppt/Step for Fine Frequency and Phase Steering (IEEE 1588 Slave)
- Zero Delay for Deterministic Phase Offset
- Robust Clock Monitoring and Status
- I²C or SPI Interface
Excellent Power Supply Noise Rejection (PSNR)
3.3V Supply With 1.8V, 2.5V, or 3.3V Outputs
Industrial Temperature Range: –40°C to +85°C