SNAS736C June   2017  – April 2019 LMX2595

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
    1.     Device Images
      1.      Simplified Schematic
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Reference Oscillator Input
      2. 7.3.2  Reference Path
        1. 7.3.2.1 OSCin Doubler (OSC_2X)
        2. 7.3.2.2 Pre-R Divider (PLL_R_PRE)
        3. 7.3.2.3 Programmable Multiplier (MULT)
        4. 7.3.2.4 Post-R Divider (PLL_R)
        5. 7.3.2.5 State Machine Clock
      3. 7.3.3  PLL Phase Detector and Charge Pump
      4. 7.3.4  N-Divider and Fractional Circuitry
      5. 7.3.5  MUXout Pin
        1. 7.3.5.1 Lock Detect
        2. 7.3.5.2 Readback
      6. 7.3.6  VCO (Voltage-Controlled Oscillator)
        1. 7.3.6.1 VCO Calibration
        2. 7.3.6.2 Determining the VCO Gain
      7. 7.3.7  Channel Divider
      8. 7.3.8  VCO Doubler
      9. 7.3.9  Output Buffer
      10. 7.3.10 Power-Down Modes
      11. 7.3.11 Phase Synchronization
        1. 7.3.11.1 General Concept
        2. 7.3.11.2 Categories of Applications for SYNC
        3. 7.3.11.3 Procedure for Using SYNC
        4. 7.3.11.4 SYNC Input Pin
      12. 7.3.12 Phase Adjust
      13. 7.3.13 Fine Adjustments for Phase Adjust and Phase SYNC
      14. 7.3.14 Ramping Function
        1. 7.3.14.1 Manual Pin Ramping
          1. 7.3.14.1.1 Manual Pin Ramping Example
        2. 7.3.14.2 Automatic Ramping
          1. 7.3.14.2.1 Automatic Ramping Example (Triangle Wave)
      15. 7.3.15 SYSREF
        1. 7.3.15.1 Programmable Fields
        2. 7.3.15.2 Input and Output Pin Formats
          1. 7.3.15.2.1 Input Format for SYNC and SysRefReq Pins
          2. 7.3.15.2.2 SYSREF Output Format
        3. 7.3.15.3 Examples
        4. 7.3.15.4 SYSREF Procedure
      16. 7.3.16 SysRefReq Pin
    4. 7.4 Device Functional Modes
    5. 7.5 Programming
      1. 7.5.1 Recommended Initial Power-Up Sequence
      2. 7.5.2 Recommended Sequence for Changing Frequencies
      3. 7.5.3 General Programming Requirements
    6. 7.6 Register Maps
      1. 7.6.1  General Registers R0, R1, & R7
        1. Table 25. Field Descriptions
      2. 7.6.2  Input Path Registers
        1. Table 26. Field Descriptions
      3. 7.6.3  Charge Pump Registers (R13, R14)
        1. Table 27. Field Descriptions
      4. 7.6.4  VCO Calibration Registers
        1. Table 28. Field Descriptions
      5. 7.6.5  N Divider, MASH, and Output Registers
        1. Table 29. Field Descriptions
      6. 7.6.6  SYNC and SysRefReq Input Pin Register
        1. Table 30. Field Descriptions
      7. 7.6.7  Lock Detect Registers
        1. Table 31. Field Descriptions
      8. 7.6.8  MASH_RESET
        1. Table 32. Field Descriptions
      9. 7.6.9  SysREF Registers
        1. Table 33. Field Descriptions
      10. 7.6.10 CHANNEL Divider And VCO Doubler Registers
        1. Table 34. Field Descriptions
      11. 7.6.11 Ramping and Calibration Fields
        1. Table 35. Field Descriptions
      12. 7.6.12 Ramping Registers
        1. 7.6.12.1 Ramp Limits
          1. Table 36. Field Descriptions
        2. 7.6.12.2 Ramping Triggers, Burst Mode, and RAMP0_RST
          1. Table 37. Field Descriptions
        3. 7.6.12.3 Ramping Configuration
          1. Table 38. Field Descriptions
      13. 7.6.13 Readback Registers
        1. Table 39. Field Descriptions
  8. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 OSCin Configuration
      2. 8.1.2 OSCin Slew Rate
      3. 8.1.3 RF Output Buffer Power Control
      4. 8.1.4 RF Output Buffer Pullup
      5. 8.1.5 Performance Comparison Between 1572 (0x0624) and 3115 (0x0C2B) for Register DBLR_IBIAS_CTRL1 (R25[15:0])
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curve
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Third-Party Products Disclaimer
      2. 11.1.2 Development Support
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
    3. 11.3 Receiving Notification of Documentation Updates
    4. 11.4 Community Resources
    5. 11.5 Trademarks
    6. 11.6 Electrostatic Discharge Caution
    7. 11.7 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

7.3.6.1 VCO Calibration

To reduce the VCO tuning gain and therefore improve the VCO phase-noise performance, the VCO frequency range is divided into several different frequency bands. The entire range, 7.5 to 15 GHz, covers an octave that allows the divider to take care of frequencies below the lower bound. This creates the need for frequency calibration to determine the correct frequency band given a desired output frequency. The frequency calibration routine is activated any time that the R0 register is programmed with the FCAL_EN = 1. It is important that a valid OSCin signal must present before VCO calibration begins.

The VCO also has an internal amplitude calibration algorithm to optimize the phase noise which is also activated any time the R0 register is programmed.

The optimum internal settings for this are temperature dependent. If the temperature is allowed to drift too much without being recalibrated, some minor phase noise degradation could result. The maximum allowable drift for continuous lock, ΔTCL, is stated in the electrical specifications. For this device, a number of 125°C means the device never loses lock if the device is operated under the Recommended Operating Conditions.

The LMX2595 allows the user to assist the VCO calibration. In general, there are three kinds of assistance, as shown in Table 5:

Table 5. Assisting the VCO Calibration Speed

ASSISTANCE LEVEL DESCRIPTION PROGRAMMABLE SETTINGS
No assist User does nothing to improve VCO calibration speed, but the user-specified VCO_SEL, VCO_DACISET_STRT and VCO_CAPCTRL_STRT values do affect the starting point of VCO calibration. For oscillation to start up properly and for VCO to calibrate correctly, TI recommends setting VCO_SEL = 7, VCO_DACISET_STRT = 300 and VCO_CAPCTRL_STRT = 183 for all frequencies except 11.9 GHz ~ 12.1 GHz. For frequencies within 11.9 ~ 12.1 GHz, user must use VCO_SEL = 4 for proper VCO calibration. QUICK_RECAL_EN=0
VCO_SEL_FORCE=0
VCO_DACISET_FORCE=0
VCO_CAPCTRL_FORCE=0
Partial assist Upon every frequency change, before the FCAL_EN bit is checked, the user provides the initial starting point for the VCO core (VCO_SEL), band (VCO_CAPCTRL_STRT), and amplitude (VCO_DACISET_STRT) based on Table 6. QUICK_RECAL_EN=0
VCO_SEL_FORCE=0
VCO_DACISET_FORCE=0
VCO_CAPCTRL_FORCE=0
Close Frequency Assist Upon initialization of the device, user enables QUICK_RECAL_EN bit.

The VCO uses the current VCO_CAPCTRL and VCO_DACISET_STRT settings as the initial starting point. 		QUICK_RECAL_EN=1
VCO_SEL_FORCE=0
VCO_DACISET_FORCE=0
VCO_CAPCTRL_FORCE=0
Full assist The user forces the VCO core (VCO_SEL), amplitude settings (VCO_DACISET), and frequency band (VCO_CAPCTRL) and manually sets the value. If the two frequency points are no more than 5MHz apart and on the same VCO core, the user can set the VCO amplitude and capcode for any frequency between those two points using linear interpolation. QUICK_RECAL_EN=0
VCO_SEL_FORCE=1
VCO_DACISET_FORCE=1
VCO_CAPCTRL_FORCE=1

To do the partial assist for the VCO calibration, follow this procedure:

  1. Determine the VCO Core

      Find a VCO Core that includes the desired VCO frequency. If at the boundary of two cores, choose one based on phase noise or performance.

  2. Calculate the VCO CapCode as follows:

      VCO_CAPCTRL_STRT = round (CCoreMin – (CCoreMin – CCoreMax) × (fVCO – fCoreMin) / (fCoreMax – fCoreMin))

  3. Get the VCO amplitude setting from Table 6.

      VCO_DACISET_STRT = round (ACoreMin + (ACoreMax – ACoreMin) × (fVCO – fCoreMin)/(fCoreMax – fCoreMin))

Table 6. VCO Core Ranges

VCO CORE fCoreMin fCoreMax CCoreMin CCoreMax ACoreMin ACoreMax
VCO1 7500 8600 164 12 299 240
VCO2 8600 9800 165 16 356 247
VCO3 9800 10800 158 19 324 224
VCO4 10800 12000 140 0 383 244
VCO5 12000 12900 183 36 205 146
VCO6 12900 13900 155 6 242 163
VCO7 13900 15000 175 19 323 244

SPACE

NOTE

In the range of 11900 MHz to 12100 MHz, VCO assistance cannot be used, and the settings must be: VCO_SEL = 4, VCO_DACISET_STRT = 300, and VCO_CAPCTRL_STRT = 1. Outside this range, in the partial assist for the VCO calibration, the VCO calibration runs. This means that if the settings are incorrect, the VCO still locks with the correct settings. The only consequence is that the calibration time might be a little longer. The closer the calibration settings are to the true final settings, the faster the VCO calibration will be.