SNAS740B October 2017 – January 2019 LMX2572
PRODUCTION DATA.
When the device comes out of the powered-down state, either by resuming the POWERDOWN bit to zero or by pulling back CE pin HIGH (if it was powered down by CE pin), it takes time for the device to acquire lock again. This wake-up time depends on LDO_DLY setting, loop bandwidth, and the state machine clock frequency (= fOSCin / 2CAL_CLK_DIV). If the loop bandwidth is greater than 20 kHz, the wake-up time could be adjusted to less than 1.5 ms with the LDO_DLY setting listed in Table 144.
STATE MACHINE CLOCK FREQUENCY | LDO_DLY |
---|---|
130 MHz ≤ f ≤ 200MHz | 8 |
80 MHz ≤ f < 130 MHz | 5 |
50 MHz ≤ f < 80 MHz | 3 |
30 MHz ≤ f < 50 MHz | 2 |
f < 30 MHz | 1 |