SNAS784B March   2019  – August 2019 LMK00804B-Q1

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
    1.     Device Images
      1.      Simplified Schematic
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. Table 1. Absolute Maximum Ratings
    2. Table 2. ESD Ratings
    3. Table 3. Recommended Operating Conditions
    4. Table 4. Thermal Information
    5. Table 5. Power Supply Characteristics
    6. Table 6. LVCMOS / LVTTL DC Electrical Characteristics
    7. Table 7. Differential Input DC Electrical Characteristics
    8. Table 8. Switching Characteristics
    9. Table 9. Pin Characteristics
    10. 6.1      Typical Characteristics
  7. 7 Parameter Measurement Information
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Clock Enable Timing
    4. 8.4 Device Functional Modes
  9. 9 Applications and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Applications
      1. 9.2.1 Output Clock Interface Circuit
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
        3. 9.2.1.3 Application Curve
          1. 9.2.1.3.1 System-Level Phase Noise and Additive Jitter Measurement
      2. 9.2.2 Input Detail
      3. 9.2.3 Input Clock Interface Circuits
    3. 9.3 Do's and Don'ts
      1. 9.3.1 Power Dissipation Calculations
      2. 9.3.2 Thermal Management
      3. 9.3.3 Recommendations for Unused Input and Output Pins
      4. 9.3.4 Input Slew Rate Considerations
  10. 10Power Supply Recommendations
    1. 10.1 Power Supply Considerations
      1. 10.1.1 Power-Supply Filtering
  11. 11Layout
    1. 11.1 Layout Guidelines
      1. 11.1.1 Ground Planes
      2. 11.1.2 Power Supply Pins
      3. 11.1.3 Differential Input Termination
      4. 11.1.4 LVCMOS Input Termination
      5. 11.1.5 Output Termination
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 Community Resources
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Table 8. Switching Characteristics

VDD = 3.3 V ± 5%, VDDO = 1.5 V ± 5%, 1.8 V ± 5%, 2.5 V ± 5%, 3.3 V ± 5% and TA = –40°C to 125°C
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
tPDLH Propagation delay,
Low-to-high 		LVCMOS_CLK(1),
CLK_P/CLK_N(2) 		–40°C to 125°C 1 2.5 ns
tSK(O) Output skew(3)(4) Measured on rising edge 35 ps
tSK(PP) Part-to-part skew(4)(5) 550 ps
tR/tF Output rise/fall time 20% to 80%, CL= 5 pF 100 310 600 ps
tJIT Additive jitter(6) f = 40 MHz,
Input slew rate = 1.25 V/ns,
12-kHz to 20-MHz integration band		 115 200 fs RMS
PNFLOOR Phase noise floor(7) f = 40 MHz,
Input slew rate = 1.25 V/ns		 10-kHz offset –151 dBc/Hz
100-kHz offset –160
1-MHz offset –162
10-MHz offset –162
20-MHz offset –162
DO Output duty cycle REF = CLK_P/CLK_N, 50% input duty cycle, f < 166 MHz 45% 55%
REF = LVCMOS_CLK, 50% input duty cycle, f > 166 MHz 42% 58%
(1) Measured from the VDD/2 of the input to the VDDO/2 of the output.
(2) Measured from the differential input crossing point to VDDO/2 of the output.
(3) Defined as skew between outputs at the same supply voltage and with equal loading conditions. Measured at VDDO/2 of the output.
(4) Parameter is defined in accordance with JEDEC Standard 65.
(5) Calculation for part-to-part skew is the difference between the fastest and slowest tPD across multiple devices, various supply voltages, operating at the same frequency, same temperature, with equal load conditions, and using the same type of inputs on each device.
(6) Buffer additive jitter: tJIT = SQRT(tJIT_SYS2 – tJIT_SOURCE2), where t JIT_SYS is the RMS jitter of the system output (source+buffer) and tJIT_SOURCE is the RMS jitter of the input source, and system output noise is not correlated to the input source noise. Additive jitter should be considered only when the input source noise floor is 3 dB or better than the buffer noise floor (PNFLOOR). This is usually the case for high-quality, ultra-low-noise oscillators. Refer to System-Level Phase Noise and Additive Jitter Measurement for input source and measurement details.
(7) Buffer phase noise floor: PNFLOOR (dBc/Hz) = 10 × log10[10^(PNSYSTEM/10) – 10^(PNSOURCE/10)], where PNSYSTEM is the phase noise floor of the system output (source+buffer) and PNSOURCE is the phase noise floor of the input source. Buffer Phase Noise Floor should be considered only when the input source noise floor is 3 dB or better than the buffer noise floor (PNFLOOR). This is usually the case for high-quality, ultra-low-noise oscillators. Refer to System-Level Phase Noise and Additive Jitter Measurement for input source and measurement details.