SNAS785D November   2019  – March 2022 LMX2694-EP

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Timing Diagrams
    8. 6.8 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Reference Oscillator Input
      2. 7.3.2  Reference Path
        1. 7.3.2.1 OSCIN Doubler (OSC_2X)
        2. 7.3.2.2 Pre-R Divider (PLL_R_PRE)
        3. 7.3.2.3 Post-R Divider (PLL_R)
      3. 7.3.3  State Machine Clock
      4. 7.3.4  PLL Phase Detector and Charge Pump
      5. 7.3.5  N Divider and Fractional Circuitry
      6. 7.3.6  MUXOUT Pin
        1. 7.3.6.1 Serial Data Output for Readback
        2. 7.3.6.2 Lock Detect Indicator Set as Type “VCOCal”
        3. 7.3.6.3 Lock Detect Indicator Set as Type “Vtune and VCOCal”
      7. 7.3.7  VCO (Voltage-Controlled Oscillator)
        1. 7.3.7.1 VCO Calibration
        2. 7.3.7.2 Determining the VCO Gain
      8. 7.3.8  Channel Divider
      9. 7.3.9  Output Buffer
      10. 7.3.10 Powerdown Modes
      11. 7.3.11 Treatment of Unused Pins
      12. 7.3.12 Phase Synchronization
        1. 7.3.12.1 General Concept
        2. 7.3.12.2 Categories of Applications for SYNC
        3. 7.3.12.3 Procedure for Using SYNC
        4. 7.3.12.4 SYNC Input Pin
      13. 7.3.13 Phase Adjust
      14. 7.3.14 Fine Adjustments for Phase Adjust and Phase SYNC
      15. 7.3.15 SYSREF
        1. 7.3.15.1 Programmable Fields
        2. 7.3.15.2 Input and Output Pin Formats
          1. 7.3.15.2.1 SYSREF Output Format
        3. 7.3.15.3 SYSREF Examples
        4. 7.3.15.4 SYSREF Procedure
    4. 7.4 Device Functional Modes
    5. 7.5 Programming
      1. 7.5.1 Recommended Initial Power-Up Sequence
      2. 7.5.2 Recommended Sequence for Changing Frequencies
    6. 7.6 Register Maps
      1. 7.6.1   R0 Register (Offset = 0x0) [reset = 0x200C]
      2. 7.6.2   R1 Register (Offset = 0x1) [reset = 0x80C]
      3. 7.6.3   R2 Register (Offset = 0x2) [reset = 0x500]
      4. 7.6.4   R3 Register (Offset = 0x3) [reset = 0x642]
      5. 7.6.5   R4 Register (Offset = 0x4) [reset = 0xA43]
      6. 7.6.6   R5 Register (Offset = 0x5) [reset = 0xC8]
      7. 7.6.7   R6 Register (Offset = 0x6) [reset = 0xC802]
      8. 7.6.8   R7 Register (Offset = 0x7) [reset = 0xB2]
      9. 7.6.9   R8 Register (Offset = 0x8) [reset = 0x2000]
      10. 7.6.10  R9 Register (Offset = 0x9) [reset = 0x604]
      11. 7.6.11  R10 Register (Offset = 0xA) [reset = 0x10F8]
      12. 7.6.12  R11 Register (Offset = 0xB) [reset = 0x18]
      13. 7.6.13  R12 Register (Offset = 0xC) [reset = 0x5001]
      14. 7.6.14  R13 Register (Offset = 0xD) [reset = 0x4000]
      15. 7.6.15  R14 Register (Offset = 0xE) [reset = 0x1E70]
      16. 7.6.16  R15 Register (Offset = 0xF) [reset = 0x64F]
      17. 7.6.17  R16 Register (Offset = 0x10) [reset = 0x80]
      18. 7.6.18  R17 Register (Offset = 0x11) [reset = 0x96]
      19. 7.6.19  R18 Register (Offset = 0x12) [reset = 0x64]
      20. 7.6.20  R19 Register (Offset = 0x13) [reset = 0x27B7]
      21. 7.6.21  R20 Register (Offset = 0x14) [reset = 0x3048]
      22. 7.6.22  R21 Register (Offset = 0x15) [reset = 0x401]
      23. 7.6.23  R22 Register (Offset = 0x16) [reset = 0x1]
      24. 7.6.24  R23 Register (Offset = 0x17) [reset = 0x7C]
      25. 7.6.25  R24 Register (Offset = 0x18) [reset = 0x71A]
      26. 7.6.26  R25 Register (Offset = 0x19) [reset = 0x624]
      27. 7.6.27  R26 Register (Offset = 0x1A) [reset = 0xDB0]
      28. 7.6.28  R27 Register (Offset = 0x1B) [reset = 0x2]
      29. 7.6.29  R28 Register (Offset = 0x1C) [reset = 0x488]
      30. 7.6.30  R29 Register (Offset = 0x1D) [reset = 0x318C]
      31. 7.6.31  R30 Register (Offset = 0x1E) [reset = 0x318C]
      32. 7.6.32  R31 Register (Offset = 0x1F) [reset = 0xC3EC]
      33. 7.6.33  R32 Register (Offset = 0x20) [reset = 0x393]
      34. 7.6.34  R33 Register (Offset = 0x21) [reset = 0x1E21]
      35. 7.6.35  R34 Register (Offset = 0x22) [reset = 0x10]
      36. 7.6.36  R35 Register (Offset = 0x23) [reset = 0x4]
      37. 7.6.37  R36 Register (Offset = 0x24) [reset = 0x70]
      38. 7.6.38  R37 Register (Offset = 0x25) [reset = 0x205]
      39. 7.6.39  R38 Register (Offset = 0x26) [reset = 0xFFFF]
      40. 7.6.40  R39 Register (Offset = 0x27) [reset = 0xFFFF]
      41. 7.6.41  R40 Register (Offset = 0x28) [reset = 0x0]
      42. 7.6.42  R41 Register (Offset = 0x29) [reset = 0x0]
      43. 7.6.43  R42 Register (Offset = 0x2A) [reset = 0x0]
      44. 7.6.44  R43 Register (Offset = 0x2B) [reset = 0x0]
      45. 7.6.45  R44 Register (Offset = 0x2C) [reset = 0x22A2]
      46. 7.6.46  R45 Register (Offset = 0x2D) [reset = 0xC622]
      47. 7.6.47  R46 Register (Offset = 0x2E) [reset = 0x7F0]
      48. 7.6.48  R47 Register (Offset = 0x2F) [reset = 0x300]
      49. 7.6.49  R48 Register (Offset = 0x30) [reset = 0x3E0]
      50. 7.6.50  R49 Register (Offset = 0x31) [reset = 0x4180]
      51. 7.6.51  R50 Register (Offset = 0x32) [reset = 0x80]
      52. 7.6.52  R51 Register (Offset = 0x33) [reset = 0x80]
      53. 7.6.53  R52 Register (Offset = 0x34) [reset = 0x420]
      54. 7.6.54  R53 Register (Offset = 0x35) [reset = 0x0]
      55. 7.6.55  R54 Register (Offset = 0x36) [reset = 0x0]
      56. 7.6.56  R55 Register (Offset = 0x37) [reset = 0x0]
      57. 7.6.57  R56 Register (Offset = 0x38) [reset = 0x0]
      58. 7.6.58  R57 Register (Offset = 0x39) [reset = 0x0]
      59. 7.6.59  R58 Register (Offset = 0x3A) [reset = 0x8001]
      60. 7.6.60  R59 Register (Offset = 0x3B) [reset = 0x1]
      61. 7.6.61  R60 Register (Offset = 0x3C) [reset = 0x3E8]
      62. 7.6.62  R61 Register (Offset = 0x3D) [reset = 0xA8]
      63. 7.6.63  R62 Register (Offset = 0x3E) [reset = 0xAE]
      64. 7.6.64  R63 Register (Offset = 0x3F) [reset = 0x0]
      65. 7.6.65  R64 Register (Offset = 0x40) [reset = 0x1388]
      66. 7.6.66  R65 Register (Offset = 0x41) [reset = 0x0]
      67. 7.6.67  R66 Register (Offset = 0x42) [reset = 0x140]
      68. 7.6.68  R67 Register (Offset = 0x43) [reset = 0x0]
      69. 7.6.69  R68 Register (Offset = 0x44) [reset = 0x3E8]
      70. 7.6.70  R69 Register (Offset = 0x45) [reset = 0x0]
      71. 7.6.71  R70 Register (Offset = 0x46) [reset = 0xC350]
      72. 7.6.72  R71 Register (Offset = 0x47) [reset = 0x80]
      73. 7.6.73  R72 Register (Offset = 0x48) [reset = 0x1]
      74. 7.6.74  R73 Register (Offset = 0x49) [reset = 0x3F]
      75. 7.6.75  R74 Register (Offset = 0x4A) [reset = 0x0]
      76. 7.6.76  R75 Register (Offset = 0x4B) [reset = 0x800]
      77. 7.6.77  R76 Register (Offset = 0x4C) [reset = 0xC]
      78. 7.6.78  R77 Register (Offset = 0x4D) [reset = 0x0]
      79. 7.6.79  R78 Register (Offset = 0x4E) [reset = 0x64]
      80. 7.6.80  R79 Register (Offset = 0x4F) [reset = 0x0]
      81. 7.6.81  R80 Register (Offset = 0x50) [reset = 0x0]
      82. 7.6.82  R81 Register (Offset = 0x51) [reset = 0x0]
      83. 7.6.83  R82 Register (Offset = 0x52) [reset = 0x0]
      84. 7.6.84  R83 Register (Offset = 0x53) [reset = 0x0]
      85. 7.6.85  R84 Register (Offset = 0x54) [reset = 0x0]
      86. 7.6.86  R85 Register (Offset = 0x55) [reset = 0x0]
      87. 7.6.87  R86 Register (Offset = 0x56) [reset = 0x0]
      88. 7.6.88  R87 Register (Offset = 0x57) [reset = 0x0]
      89. 7.6.89  R88 Register (Offset = 0x58) [reset = 0x0]
      90. 7.6.90  R89 Register (Offset = 0x59) [reset = 0x0]
      91. 7.6.91  R90 Register (Offset = 0x5A) [reset = 0x0]
      92. 7.6.92  R91 Register (Offset = 0x5B) [reset = 0x0]
      93. 7.6.93  R92 Register (Offset = 0x5C) [reset = 0x0]
      94. 7.6.94  R93 Register (Offset = 0x5D) [reset = 0x0]
      95. 7.6.95  R94 Register (Offset = 0x5E) [reset = 0x0]
      96. 7.6.96  R95 Register (Offset = 0x5F) [reset = 0x0]
      97. 7.6.97  R96 Register (Offset = 0x60) [reset = 0x0]
      98. 7.6.98  R97 Register (Offset = 0x61) [reset = 0x0]
      99. 7.6.99  R98 Register (Offset = 0x62) [reset = 0x0]
      100. 7.6.100 R99 Register (Offset = 0x63) [reset = 0x0]
      101. 7.6.101 R100 Register (Offset = 0x64) [reset = 0x0]
      102. 7.6.102 R101 Register (Offset = 0x65) [reset = 0x0]
      103. 7.6.103 R102 Register (Offset = 0x66) [reset = 0x0]
      104. 7.6.104 R103 Register (Offset = 0x67) [reset = 0x0]
      105. 7.6.105 R104 Register (Offset = 0x68) [reset = 0x0]
      106. 7.6.106 R105 Register (Offset = 0x69) [reset = 0x440]
      107. 7.6.107 R106 Register (Offset = 0x6A) [reset = 0x7]
      108. 7.6.108 R107 Register (Offset = 0x6B) [reset = 0x0]
      109. 7.6.109 R108 Register (Offset = 0x6C) [reset = 0x0]
      110. 7.6.110 R109 Register (Offset = 0x6D) [reset = 0x0]
      111. 7.6.111 R110 Register (Offset = 0x6E) [reset = 0x0]
      112. 7.6.112 R111 Register (Offset = 0x6F) [reset = 0x0]
      113. 7.6.113 R112 Register (Offset = 0x70) [reset = 0x0]
      114. 7.6.114 R113 Register (Offset = 0x71) [reset = 0x0]
      115. 7.6.115 R114 Register (Offset = 0x72) [reset = 0x0]
  8. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 OSCIN Configuration
      2. 8.1.2 OSCIN Slew Rate
      3. 8.1.3 RF Output Buffer Power Control
      4. 8.1.4 RF Output Buffer Pullup
        1. 8.1.4.1 Resistor Pullup
        2. 8.1.4.2 Inductor Pullup
        3. 8.1.4.3 Combination Pullup
      5. 8.1.5 RF Output Treatment for the Complimentary Side
        1. 8.1.5.1 Single-Ended Termination of Unused Output
        2. 8.1.5.2 Differential Termination
      6. 8.1.6 External Loop Filter
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curve
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Development Support
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
    3. 11.3 Receiving Notification of Documentation Updates
    4. 11.4 Support Resources
    5. 11.5 Trademarks
    6. 11.6 Electrostatic Discharge Caution
    7. 11.7 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

7.6 Register Maps

REG.DATA[15:0]POR
1514131211109876543210
R00VCO_PHASE_
SYNC		1000OUT_MUTEFCAL_HPFD_ADJ001FCAL_ENMUXOUT_
LD_SEL		RESETPOWER
DOWN		0x200C
R1000010000000MUXOUT_CTRLCAL_CLK_DIV0x80C
R200000101000000000x500
R300000110010000100x642
R400001110010000110xA43
R500000011111010000xC8
R601111000000000100xC802
R700000000101100100xB2
R80VCO_
DACISET_
FORCE		10VCO_
CAPCTRL_
FORCE		000000000000x2000
R9000OSC_2X0110000001000x604
R1000010000110110000x10F8
R110000PLL_R10000x18
R1201010000PLL_R_PRE0x5001
R1301000000000000000x4000
R14000111100CPG00000x1E70
R1500000110010011110x64F
R160000000VCO_DACISET0x80
R1700000001001011000x96
R1800000000011001000x64
R1900100111VCO_CAPCTRL0x27B7
R2011VCO_SELVCO_SEL_
FORCE		00010010000x3048
R2100000100000000010x401
R2200000000000000010x1
R2300000000011111000x7C
R2400000111000110100x71A
R2500000110001001000x624
R2600001101101100000xDB0
R2700000000000000100x2
R2800000100100010000x488
R2900110001100011000x318C
R3000110001100011000x318C
R310SEG1_EN000011111011000xC3EC
R3200000011100100110x393
R3300011110001000010x1E21
R340000000000000PLL_N[18:16]0x10
R3500000000000001000x4
R36PLL_N[15:0]0x70
R3710PFD_DLY_SEL000001000x205
R38PLL_DEN[31:16]0xFFFF
R39PLL_DEN[15:0]0xFFFF
R40MASH_SEED[31:16]0x0
R41MASH_SEED[15:0]0x0
R42PLL_NUM[31:16]0x0
R43PLL_NUM[15:0]0x0
R4400OUTA_PWROUTB_
PD		OUTA_
PD		MASH_
RESET_N		00MASH_ORDER0x22A2
R45110OUTA_MUX00011OUTB_PWR0xC622
R4600000111111111OUTB_MUX0x7F0
R4700000011000000000x300
R4800000011000000000x3E0
R4901000001100000000x4180
R5000000000000000000x80
R5100000000100000000x80
R5200000100001000000x420
R5300000000000000000x0
R5400000000000000000x0
R5500000000000000000x0
R5600000000000000000x0
R5700000000001000000x0
R58INPIN_
IGNORE		0000000000000010x8001
R59000000000000000LD_TYPE0x1
R60LD_DLY0x3E8
R6100000000101010000xA8
R6200000011001000100xAE
R6300000000000000000x0
R6400010011100010000x1388
R6500000000000000000x0
R6600000001111101000x140
R6700000000000000000x0
R6800000011111010000x3E8
R69MASH_RST_COUNT[31:16]0x0
R70MASH_RST_COUNT[15:0]0xC350
R7100000000SYSREF_DIV_PRESYSREF_
PULSE		SYSREF_
EN		SYSREF_
REPEAT		000x80
R7200000SYSREF_DIV0x1
R730000JESD_DAC2_CTRLJESD_DAC1_CTRL0x3F
R74SYSREF_PULSE_CNTJESD_DAC4_CTRLJESD_DAC3_CTRL0x0
R7500001CHDIV0000000x800
R7600000000000011000xC
R7700000000000000000x0
R7800000000011001000x64
R7900000000000000000x0
R8000000000000000000x0
R8100000000000000000x0
R8200000000000000000x0
R8300000000000000000x0
R8400000000000000000x0
R8500000000000000000x0
R8600000000000000000x0
R8700000000000000000x0
R8800000000000000000x0
R8900000000000000000x0
R9000000000000000000x0
R9100000000000000000x0
R9200000000000000000x0
R9300000000000000000x0
R9400000000000000000x0
R9500000000000000000x0
R9600000000000000000x0
R9700000000000000000x0
R9800000000000000000x0
R9900000000000000000x0
R10000000000000000000x0
R10100000000000000000x0
R10200000000000000000x0
R10300000000000000000x0
R10400000000000000000x0
R10500000000000000000x440
R10600000000000000000x7
R10700000000000000000x0
R10800000000000000000x0
R10900000000000000000x0
R11000000rb_LD_VTUNE0rb_VCO_SEL000000x0
R11100000000rb_VCO_CAPCTRL0x0
R1120000000rb_VCO_DACISET0x0
R11300000000000000000x0
R11400000000000000000x0
Table 7-18 Device Registers
OffsetAcronymRegister NameSection
0x0R0Go
0x1R1Go
0x2R2Go
0x3R3Go
0x4R4Go
0x5R5Go
0x6R6Go
0x7R7Go
0x8R8Go
0x9R9Go
0xAR10Go
0xBR11Go
0xCR12Go
0xDR13Go
0xER14Go
0xFR15Go
0x10R16Go
0x11R17Go
0x12R18Go
0x13R19Go
0x14R20Go
0x15R21Go
0x16R22Go
0x17R23Go
0x18R24Go
0x19R25Go
0x1AR26Go
0x1BR27Go
0x1CR28Go
0x1DR29Go
0x1ER30Go
0x1FR31Go
0x20R32Go
0x21R33Go
0x22R34Go
0x23R35Go
0x24R36Go
0x25R37Go
0x26R38Go
0x27R39Go
0x28R40Go
0x29R41Go
0x2AR42Go
0x2BR43Go
0x2CR44Go
0x2DR45Go
0x2ER46Go
0x2FR47Go
0x30R48Go
0x31R49Go
0x32R50Go
0x33R51Go
0x34R52Go
0x35R53Go
0x36R54Go
0x37R55Go
0x38R56Go
0x39R57Go
0x3AR58Go
0x3BR59Go
0x3CR60Go
0x3DR61Go
0x3ER62Go
0x3FR63Go
0x40R64Go
0x41R65Go
0x42R66Go
0x43R67Go
0x44R68Go
0x45R69Go
0x46R70Go
0x47R71Go
0x48R72Go
0x49R73Go
0x4AR74Go
0x4BR75Go
0x4CR76Go
0x4DR77Go
0x4ER78Go
0x4FR79Go
0x50R80Go
0x51R81Go
0x52R82Go
0x53R83Go
0x54R84Go
0x55R85Go
0x56R86Go
0x57R87Go
0x58R88Go
0x59R89Go
0x5AR90Go
0x5BR91Go
0x5CR92Go
0x5DR93Go
0x5ER94Go
0x5FR95Go
0x60R96Go
0x61R97Go
0x62R98Go
0x63R99Go
0x64R100Go
0x65R101Go
0x66R102Go
0x67R103Go
0x68R104Go
0x69R105Go
0x6AR106Go
0x6BR107Go
0x6CR108Go
0x6DR109Go
0x6ER110Go
0x6FR111Go
0x70R112Go
0x71R113Go
0x72R114Go

Complex bit access types are encoded to fit into small table cells. Table 7-19 shows the codes that are used for access types in this section.

Table 7-19 Device Access Type Codes
Access TypeCodeDescription
Read Type
RRRead
Write Type
WWWrite
Reset or Default Value
-nValue after reset or the default value