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CDCDB2000 DB2000QL-Compliant 20-Output Clock Buffer for PCIe Gen 1 to Gen 5
SNAS787B
November 2019 – October 2024
CDCDB2000
PRODUCTION DATA
CONTENTS
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CDCDB2000 DB2000QL-Compliant 20-Output Clock Buffer for PCIe Gen 1 to Gen 5
1
1
Features
2
Applications
3
Description
4
Pin Configuration and Functions
5
Specifications
5.1
Absolute Maximum Ratings
5.2
ESD Ratings
5.3
Recommended Operating Conditions
5.4
Thermal Information
5.5
Electrical Characteristics
5.6
Timing Requirements
5.7
Typical Characteristics
6
Detailed Description
6.1
Overview
6.2
Functional Block Diagram
6.3
Feature Description
6.3.1
Output Enable Control
6.3.2
SMBus
6.3.2.1
SMBus Address Assignment
6.3.3
Side-Band Interface
6.4
Device Functional Modes
6.4.1
CKPWRGD_PD# Function
6.4.2
OE[12:5]# and SMBus Output Enables
6.5
Programming
6.5.1
SMBus
6.5.2
SBI
7
Register Maps
7.1
CDCDB2000 Registers
8
Application and Implementation
8.1
Application Information
8.2
Typical Application
8.2.1
Design Requirements
8.2.2
Detailed Design Procedure
8.2.2.1
Output Enable Control Method
8.2.2.2
SMBus Address
8.2.3
Application Curve
8.3
Power Supply Recommendations
8.4
Layout
8.4.1
Layout Guidelines
8.4.2
Layout Examples
9
Device and Documentation Support
9.1
Device Support
9.1.1
TICS Pro
9.2
Receiving Notification of Documentation Updates
9.3
Support Resources
9.4
Trademarks
9.5
Electrostatic Discharge Caution
9.6
Glossary
10
Revision History
11
Mechanical, Packaging, and Orderable Information
IMPORTANT NOTICE
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Data Sheet
CDCDB2000 DB2000QL-Compliant 20-Output Clock Buffer for PCIe Gen 1 to Gen 5
1
Features
20 LP-HCSL outputs with integrated 85-Ω output terminations
8 hardware output enable (OE#) controls
Additive phase jitter after DB2000QL filter:
< 0.08ps rms
Supports PCIe Gen 4 and Gen 5 Common Clock (CC) and Individual Reference (IR) architectures
Spread spectrum-compatible
Cycle-to-cycle jitter: < 50 ps
Output-to-output skew: < 50 ps
Input-to-output delay: < 3 ns
3.3-V core and IO supply voltages
Hardware-controlled low power mode (PD#)
Side-Band Interface (SBI) for output control in PD# mode
9 selectable SMBus addresses
Power consumption: < 600 mW
6-mm × 6-mm, 80-pin TLGA/GQFN package
2
Applications
Microserver & tower server
Storage area network & host bus adapter card
Network attached storage
Hardware accelerator
