SNAS806 September 2020 TPL1401
PRODUCTION DATA
For a single update, the TPL1401 requires a start condition, a valid I2C address byte, a command byte, and two data bytes, as listed in Table 7-3.
MSB | .... | LSB | ACK | MSB | ... | LSB | ACK | MSB | ... | LSB | ACK | MSB | ... | LSB | ACK |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
Address (A) byte Section 7.5.3 |
Command byte Section 7.5.4 |
Data byte - MSDB Section 8.2.3 | Data byte - LSDB Section 8.2.3 | ||||||||||||
DB [31:24] | DB [23:16] | DB [15:8] | DB [7:0] |
After each byte is received, the TPL1401 acknowledges the byte by pulling the SDA line low during the high period of a single clock pulse, as shown in Figure 7-5. These four bytes and acknowledge cycles make up the 36 clock cycles required for a single update to occur. A valid I2C address byte selects the TPL1401 device.
The command byte sets the operating mode of the selected TPL1401. For a data update to occur when the operating mode is selected by this byte, the TPL1401 must receive two data bytes: the most significant data byte (MSDB) and least significant data byte (LSDB). The TPL1401 performs an update on the falling edge of the acknowledge signal that follows the LSDB.
When using fast mode (clock = 400 kHz), the maximum digipot update rate is limited to 10 kSPS. Using the fast mode plus (clock = 1 MHz), the maximum digipot update rate is limited to 25 kSPS. When a stop condition is received, the TPL1401 releases the I2C bus and awaits a new start condition.