SNAS826E April 2022 – April 2024 LMK6C , LMK6D , LMK6H , LMK6P
PRODUCTION DATA
- 1
- 1 Features
- 2 Applications
- 3 Description
- 4 Device Ordering Information
- 5 Pin Configuration and Functions
- 6 Specifications
- 7 Parameter Measurement Information
- 8 Detailed Description
- 9 Application and Implementation
- 10Device and Documentation Support
- 11Revision History
- 12Mechanical, Packaging, and Orderable Information
8.3.4 Clock Output Interfacing and Termination
These figures show the recommended output interfacing and termination circuits.
Figure 8-1 LMK6C Output to LVCMOS Receiver
Figure 8-2 LMK6D Output DC-Coupled to LVDS Receiver With
Internal Termination/Biasing
Figure 8-3 LMK6D Output AC Coupled to LVDS Receiver With
Internal Termination/Biasing
Figure 8-4 LMK6P Output DC-Coupled to LVPECL Receiver
With External Termination/Biasing (T-Network)
Table 8-3 LMK6P T-Network DC-Coupled
Resistor Values
| SUPPLY (V) | R1 (Ω) | R2 (Ω) |
|---|---|---|
| 3.3 | 133 | 82 |
| 2.5 | 250 | 62.5 |
| 1.8 | 450 | 56.5 |
Figure 8-5 LMK6P Output AC-Coupled to LVPECL Receiver
With External Termination/Biasing (T-Network)
Table 8-4 LMK6P T-Network AC-Coupled
Resistor Values
| SUPPLY (V) | Rp (Ω) | R1 (Ω) | R2 (Ω) |
|---|---|---|---|
| 3.3 | 207.5 | 133 | 82 |
| 2.5 | 112.5 | 250 | 62.5 |
| 1.8 | 83.3 | 450 | 56.6 |
Figure 8-6 LMK6P Output DC-Coupled to LVPECL Receiver
With External Termination/Biasing (Y-Network)
Table 8-5 LMK6P Y-Network DC-Coupled
Resistor Values
| SUPPLY (V) | R1 (Ω) | R2 (Ω) |
|---|---|---|
| 3.3 | 50 | 78.8 |
| 2.5 | 50 | 31.3 |
| 1.8 | 50 | 16.7 |
Figure 8-7 LMK6P Output AC-Coupled to LVPECL Receiver
With External Termination/Biasing (Y-Network)
Table 8-6 LMK6P Y-Network AC-Coupled
Resistor Values
| SUPPLY (V) | Rp (Ω) | R1 (Ω) | R2 (Ω) |
|---|---|---|---|
| 3.3 | 207.5 | 50 | 78.8 |
| 2.5 | 112.5 | 50 | 31.3 |
| 1.8 | 83.3 | 50 | 16.7 |
Figure 8-8 LMK6H Output to HCSL Receiver With External
Termination
Figure 8-9 LMK6H Output AC-Coupled to HCSL Receiver
With External Termination