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  • LMX2624-SP 5MHz to 28GHz Wideband Synthesizer With Phase Synchronization and JESD204B/C Support

    • SNAS849 December   2024 LMX2624-SP

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  • LMX2624-SP 5MHz to 28GHz Wideband Synthesizer With Phase Synchronization and JESD204B/C Support
  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Timing Requirements
    7. 5.7 Timing Diagrams
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1  Reference Oscillator Input
      2. 6.3.2  Reference Path
        1. 6.3.2.1 OSCin Doubler (OSC_2X)
        2. 6.3.2.2 Pre-R Divider (PLL_R_PRE)
        3. 6.3.2.3 Post-R Divider (PLL_R)
      3. 6.3.3  State Machine Clock
      4. 6.3.4  PLL Phase Detector and Charge Pump
      5. 6.3.5  N Divider and Fractional Circuitry
      6. 6.3.6  MUXout Pin
        1. 6.3.6.1 Serial Data Output for Readback
        2. 6.3.6.2 Lock Detect Indicator Set as Type “VCOcal” or "Vtune and VCOcal"
      7. 6.3.7  VCO (Voltage-Controlled Oscillator)
        1. 6.3.7.1 VCO Calibration
          1. 6.3.7.1.1 Double Buffering (Shadow Registers)
        2. 6.3.7.2 Watchdog Feature
        3. 6.3.7.3 RECAL Feature
        4. 6.3.7.4 Determining the VCO Gain
      8. 6.3.8  Channel Divider
      9. 6.3.9  Output Mute Pin and Ping Pong Approaches
      10. 6.3.10 Output Frequency Doubler
      11. 6.3.11 Output Buffer
      12. 6.3.12 Power-Down Modes
      13. 6.3.13 Pin-Mode Integer Frequency Generation
      14. 6.3.14 Treatment of Unused Pins
      15. 6.3.15 Phase Synchronization
        1. 6.3.15.1 General Concept
        2. 6.3.15.2 Categories of Applications for SYNC
        3. 6.3.15.3 Procedure for Using SYNC
        4. 6.3.15.4 SYNC Input Pin
      16. 6.3.16 Phase Adjust
      17. 6.3.17 Fine Adjustments for Phase Adjust and Phase SYNC
      18. 6.3.18 SYSREF
        1. 6.3.18.1 Programmable Fields
        2. 6.3.18.2 Input and Output Pin Formats
          1. 6.3.18.2.1 SYSREF Output Format
        3. 6.3.18.3 Examples
        4. 6.3.18.4 SYSREF Procedure
    4. 6.4 Device Functional Modes
    5. 6.5 Programming
      1. 6.5.1 Recommended Initial Power-Up Sequence
      2. 6.5.2 Recommended Sequence for Changing Frequencies
  8. 7 Register Maps
    1. 7.1 Device Registers
  9. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 OSCin Configuration
      2. 8.1.2 OSCin Slew Rate
      3. 8.1.3 RF Output Buffer Power Control
      4. 8.1.4 RF Output Buffer Pullup
      5. 8.1.5 RF Output Treatment for the Complimentary Side
        1. 8.1.5.1 Single-ended Termination of Unused Output
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curve
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
      3. 8.4.3 Footprint Example on PCB Layout
      4. 8.4.4 Radiation Environments
        1. 8.4.4.1 Total Ionizing Dose
        2. 8.4.4.2 Single Event Effect
  10. 9 Device and Documentation Support
    1. 9.1 Device Support
      1. 9.1.1 Development Support
    2. 9.2 Documentation Support
      1. 9.2.1 Related Documentation
    3. 9.3 Receiving Notification of Documentation Updates
    4. 9.4 Support Resources
    5. 9.5 Trademarks
    6. 9.6 Electrostatic Discharge Caution
    7. 9.7 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information
    1. 11.1 Engineering Samples
    2. 11.2 Package Option Addendum
    3. 11.3 Tape and Reel Information
  13. IMPORTANT NOTICE
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Data Sheet

LMX2624-SP 5MHz to 28GHz Wideband Synthesizer With Phase Synchronization and JESD204B/C Support

1 Features

  • SMD 5962R2321001PXE
    • Total ionizing dose 100Krad (ELDRS-free)
    • Single event latch-up (SEL) immune up to 75MeV-cm2/mg
    • Single event functional interrupt (SEFI) immune up to 75MeV-cm2/mg
  • Wide band frequency synthesizer : 5MHz to 28GHz output frequency
  • –101dBc/Hz phase noise at 100kHz offset with 24GHz carrier
  • 60fs RMS jitter at 24GHz (1kHz to 300MHz)
  • Programmable output power
  • PLL key specifications:
    • Figure of merit: –236dBc/Hz
    • Normalized 1/f noise: –129dBc/Hz
    • Up to 200MHz phase detector frequency
  • Synchronization of output phase across multiple devices
  • Independent mute pins for RFoutA and RFoutB with 200ns mute/unmute time
  • Support for SYSREF with 9ps resolution programmable delay
  • 3.3V single power supply operation
  • Pin-mode: Pin configurable N divider and output divider in Integer PLL mode
  • 10 × 10mm² 64 lead QFP package
  • Operating temperature range: –55°C to +125°C
  • Supported by PLLatinum™ Simulator design tool

2 Applications

  • Space communications payload up to Ku/Ka bands
  • Space radar systems
  • Command and Data handling system
  • High-speed data converter clocking (supports JESD204B/C)
  • Local Oscillator for Mixer up to 28GHz frequency

3 Description

The LMX2624-SP is a high performance wideband phase-locked loop (PLL) with integrated voltage controlled oscillator (VCO) and voltage regulators that can output any frequency from 5MHz and 28GHz. The VCO on this device covers an entire octave so the frequency coverage is complete down to 5MHz. The high performance PLL with a figure of merit of –236dBc/Hz and high phase detector frequency can attain very low in-band noise and integrated jitter.

The LMX2624-SP allows users to synchronize the output of multiple instances of the device. This means that deterministic phase can be obtained from a device in use cases including the one with fractional engine or output divider enabled. The device also adds support for either generating or repeating SYSREF (compliant to JESD204B/C standard), making the device designed for low-noise clock source for high-speed data converters.

This device is fabricated in Texas Instruments' advanced BiCMOS process and is available in a 64-lead QFP plastic package.

Package Information
PART NUMBER GRADE PACKAGE(1) PACKAGE SIZE(2)
LMX2624-SP QML-P QFP 64-pin 10mm × 10mm
(1) For more information, see Section 11.
(2) The package size (length × width) is a nominal value and includes pins, where applicable.
LMX2624-SP Functional Block Diagram Functional Block Diagram

 
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