SNAS855D November   2023  – June 2024 LMKDB1108 , LMKDB1120 , LMKDB1204

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 SMBus Timing Requirements
    7. 6.7 SBI Timing Requirements
    8. 6.8 Timing Diagrams
    9. 6.9 Typical Characteristics
  8. 7 Parameter Measurement Information
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Input Features
        1. 8.3.1.1 Running Input Clocks When Device is Powered Off
        2. 8.3.1.2 Fail-Safe Inputs
        3. 8.3.1.3 Input Configurations
          1. 8.3.1.3.1 Internal Termination for Clock Inputs
          2. 8.3.1.3.2 AC-Coupled or DC-Coupled Clock Inputs
      2. 8.3.2 Flexible Power Sequence
        1. 8.3.2.1 PWRDN# Assertion and Deassertion
        2. 8.3.2.2 OE# Assertion and Deassertion
        3. 8.3.2.3 PWRGD Assertion
        4. 8.3.2.4 Clock Input and PWRGD/PWRDN# Behaviors When Device Power is Off
      3. 8.3.3 LOS and OE
        1. 8.3.3.1 Additional OE# Pins for LMKDB1120 and Backward Compatibility
        2. 8.3.3.2 Synchronous OE
        3. 8.3.3.3 OE Control
        4. 8.3.3.4 Automatic Output Disable
        5. 8.3.3.5 LOS Detection
      4. 8.3.4 Output Features
        1. 8.3.4.1 Output Banks
        2. 8.3.4.2 Double Termination
        3. 8.3.4.3 Programmable Output Slew Rate
          1. 8.3.4.3.1 Slew Rate Control through Pin
          2. 8.3.4.3.2 Slew Rate Control through SMBus
        4. 8.3.4.4 Programmable Output Swing
        5. 8.3.4.5 Accurate Output Impedance
        6. 8.3.4.6 Programmable Output Impedance
    4. 8.4 Device Functional Modes
      1. 8.4.1 SMBus Mode
      2. 8.4.2 SBI Mode
      3. 8.4.3 Pin Mode
  10. 9 Register Maps
    1. 9.1 LMKDB1120 Registers
    2. 9.2 LMKDB1108 Registers
    3. 9.3 LMKDB1104 Registers
    4. 9.4 LMKDB1204 Registers
  11. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
      3. 10.2.3 Application Curves
    3. 10.3 Power Supply Recommendations
    4. 10.4 Layout
      1. 10.4.1 Layout Guidelines
      2. 10.4.2 Layout Example
  12. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 Support Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  13. 12Revision History
  14. 13Mechanical, Packaging, and Orderable Information

9.4 LMKDB1204 Registers

Table 9-77 lists the memory-mapped registers for the LMKDB1204 registers. All register offset addresses not listed in Table 9-77 must be considered as reserved locations and the register contents must not be modified.

Table 9-77 LMKDB1204 Registers
OffsetAcronymRegister NameSection
0hR0Output Enable Control for CLK2 and CLK3Section 9.4.1
1hR1Output Enable Control for CLK0 and CLK1Section 9.4.2
2hR2OE Pin Readback for CLK2 and CLK3Section 9.4.3
3hR3OE Pin Readback for CLK0 and CLK1Section 9.4.4
4hR4CLKIN1 AOD Enable ControlSection 9.4.5
5hR5Device InfoSection 9.4.6
6hR6Device Info (cont.)Section 9.4.7
7hR7SMBus Byte CounterSection 9.4.8
11hR17Output AmplitudeSection 9.4.9
12hR18Input Configuration, Save Config in PD, SMB SDATA Monitoring, and LOS ReadbackSection 9.4.10
14hR20Output Slew Rate Select MSB for CLK2 and CLK3Section 9.4.11
15hR21Output Slew Rate Select MSB for CLK0 and CLK1Section 9.4.12
24hR36CLKIN0 AOD Enable ControlSection 9.4.13
26hR38Non-clearable SMBUS Write LockSection 9.4.14
27hR39LOS Event Status and Clearable SMBus Write LockSection 9.4.15
2BhR43CLKIN Source SelectSection 9.4.16
5BhR91Slew Rate Speed Options 1 and 2 AssignmentsSection 9.4.17
5ChR92Slew Rate Speed Options 3 and 4 AssignmentsSection 9.4.18
5DhR93CLKIN0 AC/DC coupled SelectionSection 9.4.19
62hR98Output Slew Rate Select LSB for CLK0 and CLK1Section 9.4.20
63hR99Output Slew Rate Select LSB for CLK2 and CLK3Section 9.4.21

Complex bit access types are encoded to fit into small table cells. Table 9-78 shows the codes that are used for access types in this section.

Table 9-78 LMKDB1204 Access Type Codes
Access TypeCodeDescription
Read Type
RRRead
Write Type
WWWrite
W1CW
1C		Write
1 to clear
Reset or Default Value
-nValue after reset or the default value

9.4.1 R0 Register (Offset = 0h) [Reset = 28h]

R0 is shown in Table 9-79.

Return to the Table 9-77.

Table 9-79 R0 Register Field Descriptions
BitFieldTypeResetDescription
7:6RESERVEDR0h Reserved
5CLK_EN_1R/W1h Output Enable for CLK1
0h = Output Disabled (low/low)
1h = Output Enabled
4RESERVEDR0h Reserved
3CLK_EN_0R/W1h Output Enable for CLK0
0h = Output Disabled (low/low)
1h = Output Enabled
2:0RESERVEDR0h Reserved

9.4.2 R1 Register (Offset = 1h) [Reset = 14h]

R1 is shown in Table 9-80.

Return to the Table 9-77.

Table 9-80 R1 Register Field Descriptions
BitFieldTypeResetDescription
7:5RESERVEDR0h Reserved
4CLK_EN_3R/W1h Output Enable for CLK3
0h = Output Disabled (low/low)
1h = Output Enabled
3RESERVEDR0h Reserved
2CLK_EN_2R/W1h Output Enable for CLK2
0h = Output Disabled (low/low)
1h = Output Enabled
1:0RESERVEDR0h Reserved

9.4.3 R2 Register (Offset = 2h) [Reset = 00h]

R2 is shown in Table 9-81.

Return to the Table 9-77.

Table 9-81 R2 Register Field Descriptions
BitFieldTypeResetDescription
7:6RESERVEDR0h Reserved
5RB_OEb_1R0h Status of OEb1
4RESERVEDR0h Reserved
3RB_OEb_0R0h Status of OEb0
2:0RESERVEDR0h Reserved

9.4.4 R3 Register (Offset = 3h) [Reset = 00h]

R3 is shown in Table 9-82.

Return to the Table 9-77.

Table 9-82 R3 Register Field Descriptions
BitFieldTypeResetDescription
7:5RESERVEDR0h Reserved
4RB_OEb_3R0h Status of OEb3
3RESERVEDR0h Reserved
2RB_OEb_2R0h Status of OEb2
1:0RESERVEDR0h Reserved

9.4.5 R4 Register (Offset = 4h) [Reset = 10h]

R4 is shown in Table 9-83.

Return to the Table 9-77.

Table 9-83 R4 Register Field Descriptions
BitFieldTypeResetDescription
7:5RESERVEDR0h Reserved
4CLKIN1_AOD_ENABLER/W1h Enable automatic output disable (AOD) for CLKIN1 to low/low when LOS event is detected. Refer to section "Automatic Output Disable" for more information.
0h = Inactive
1h = Active
3:0RESERVEDR0h Reserved

9.4.6 R5 Register (Offset = 5h) [Reset = 0Ah]

R5 is shown in Table 9-84.

Return to the Table 9-77.

Table 9-84 R5 Register Field Descriptions
BitFieldTypeResetDescription
7:4REV_IDR0h Revision ID
3:0VENDOR_IDRAh Vendor ID

9.4.7 R6 Register (Offset = 6h) [Reset = 24h]

R6 is shown in Table 9-85.

Return to the Table 9-77.

Table 9-85 R6 Register Field Descriptions
BitFieldTypeResetDescription
7:0DEV_IDR24h Device ID

9.4.8 R7 Register (Offset = 7h) [Reset = 07h]

R7 is shown in Table 9-86.

Return to the Table 9-77.

Table 9-86 R7 Register Field Descriptions
BitFieldTypeResetDescription
7:5RESERVEDR0h Reserved
4:0SMBUS_BCR/W7h SMBUS Block Read Byte Count

9.4.9 R17 Register (Offset = 11h) [Reset = 66h]

R17 is shown in Table 9-87.

Return to the Table 9-77.

Table 9-87 R17 Register Field Descriptions
BitFieldTypeResetDescription
7:4AMP_BANK1R/W6h Global Differential output Control,approximately 0.6V to 1V 25mV/step (default = 0.75V)
0h = 600 mV
1h = 625 mV
2h = 650 mV
3h = 675 mV
4h = 700 mV
5h = 725 mV
6h = 750 mV
7h = 775 mV
8h = 800 mV
9h = 825 mV
Ah = 850 mV
Bh = 875 mV
Ch = 900 mV
Dh = 925 mV
Eh = 950 mV
Fh = 975 mV
3:0AMP_BANK0R/W6h Global Differential output Control,approximately 0.6V to 1V 25mV/step (default = 0.75V)
0h = 600 mV
1h = 625 mV
2h = 650 mV
3h = 675 mV
4h = 700 mV
5h = 725 mV
6h = 750 mV
7h = 775 mV
8h = 800 mV
9h = 825 mV
Ah = 850 mV
Bh = 875 mV
Ch = 900 mV
Dh = 925 mV
Eh = 950 mV
Fh = 975 mV

9.4.10 R18 Register (Offset = 12h) [Reset = 0Ah]

R18 is shown in Table 9-88.

Return to the Table 9-77.

Table 9-88 R18 Register Field Descriptions
BitFieldTypeResetDescription
7RX_CLKIN1_EN_AC_INPUTR/W0h Enable receiver bias when CLKIN1 is AC coupled
0h = DC Coupled Input
1h = AC Coupled Input
6RX_CLKIN1_EN_RTERMR/W0h Enable termination resistors on CLKIN1
0h = Input termination inactive
1h = Input termination active
5RX_CLKIN0_EN_RTERMR/W0h Enable termination resistors on CLKIN0
0h = Input termination inactive
1h = Input termination active
4RESERVEDR0h Reserved
3PD_RESTOREBR1h Save configuration in powerdown
0h = Config Cleared
1h = Config Saved
2RESERVEDR0h Reserved
1SDATA_TIMEOUT_ENR1h Enable SMBus SDATA time out monitoring
0h = Disable SDATA timeout
1h = Enable SDATA timeout
0LOSb_RBR0h Real time read back of loss detect block output
0h = LOS Event Detected
1h = LOS Event Not-Detected

9.4.11 R20 Register (Offset = 14h) [Reset = 28h]

R20 is shown in Table 9-89.

Return to the Table 9-77.

Table 9-89 R20 Register Field Descriptions
BitFieldTypeResetDescription
7:6RESERVEDR0h Reserved
5SLEWRATE_SEL_CLK1_MSBR/W1h MSB CLK1 slew rate select
4RESERVEDR0h Reserved
3SLEWRATE_SEL_CLK0_MSBR/W1h MSB CLK0 slew rate select
2:0RESERVEDR0h Reserved

9.4.12 R21 Register (Offset = 15h) [Reset = 14h]

R21 is shown in Table 9-90.

Return to the Table 9-77.

Table 9-90 R21 Register Field Descriptions
BitFieldTypeResetDescription
7:5RESERVEDR0h Reserved
4SLEWRATE_SEL_CLK3_MSBR/W1h MSB CLK3 slew rate select
3RESERVEDR0h Reserved
2SLEWRATE_SEL_CLK2_MSBR/W1h MSB CLK2 slew rate select
1:0RESERVEDR0h Reserved

9.4.13 R36 Register (Offset = 24h) [Reset = 09h]

R36 is shown in Table 9-91.

Return to the Table 9-77.

Table 9-91 R36 Register Field Descriptions
BitFieldTypeResetDescription
7:4RESERVEDR0h Reserved
3CLKIN0_AOD_ENABLER/W1h Enable automatic output disable (AOD) for CLKIN0 to low/low when LOS event is detected. Refer to section "Automatic Output Disable" for more information.
0h = Inactive
1h = Active
2:0RESERVEDR0h Reserved

9.4.14 R38 Register (Offset = 26h) [Reset = 00h]

R38 is shown in Table 9-92.

Return to the Table 9-77.

Table 9-92 R38 Register Field Descriptions
BitFieldTypeResetDescription
7:1RESERVEDR0h Reserved
0WRITE_LOCKR0h Non-clearable SMBus Write Lock bit. When written to one, the SMBus control registers cannot be written to. This bit can only be cleared by recycling power.
0h = SMBus Not Locked for Writing
1h = SMBus Locked for Writing

9.4.15 R39 Register (Offset = 27h) [Reset = 00h]

R39 is shown in Table 9-93.

Return to the Table 9-77.

Table 9-93 R39 Register Field Descriptions
BitFieldTypeResetDescription
7:2RESERVEDR0h Reserved
1LOS_EVTR0h LOS Event Status. When high, indicates that a LOS event is detected. Can be cleared by writing a 1.
0h = Not LOS Event Detected
1h = LOS Event Detected
0WRITE_LOCK_RW1CR/W1C0h Clearable SMBus Write Lock bit. When written to one, the SMBus control registers can not be written to. This bit can be cleared by writing a 1.
0h = SMBus Not Locked for Writing
1h = SMBus Locked for Writing

9.4.16 R43 Register (Offset = 2Bh) [Reset = 00h]

R43 is shown in Table 9-94.

Return to the Table 9-77.

Table 9-94 R43 Register Field Descriptions
BitFieldTypeResetDescription
7:6RESERVEDR0h Reserved
5:4CLKIN_SELR/W0h CLKIN Source Select
0h = All outputs come from CLKIN0
1h = CLKIN0 inputs go to BANK0 and CLKIN1 inputs go to BANK1
2h = Invalid
3h = All outputs come from CLKIN1
3:0RESERVEDR0h Reserved

9.4.17 R91 Register (Offset = 5Bh) [Reset = 60h]

R91 is shown in Table 9-95.

Return to the Table 9-77.

Table 9-95 R91 Register Field Descriptions
BitFieldTypeResetDescription
7:4SLEWRATE_OPT_2R/W6h There are four register assignments each storing a slew rate value (chosen out of the 16 available slew rate values). This register bits relate to the 2nd option. Go to Programmable Output Slew Rate section for more information.
0h = 0 (fastest)
1h = 1
2h = 2
3h = 3
4h = 4
5h = 5
6h = 6
7h = 7
8h = 8
9h = 9
Ah = 10
Bh = 11
Ch = 12
Dh = 13
Eh = 14
Fh = 15 (slowest)
3:0SLEWRATE_OPT_1R/W0h There are four register assignments each storing a slew rate value (chosen out of the 16 available slew rate values). This register bits relate to the 1st option. Go to Programmable Output Slew Rate section for more information.
0h = 0 (fastest)
1h = 1
2h = 2
3h = 3
4h = 4
5h = 5
6h = 6
7h = 7
8h = 8
9h = 9
Ah = 10
Bh = 11
Ch = 12
Dh = 13
Eh = 14
Fh = 15 (slowest)

9.4.18 R92 Register (Offset = 5Ch) [Reset = FAh]

R92 is shown in Table 9-96.

Return to the Table 9-77.

Table 9-96 R92 Register Field Descriptions
BitFieldTypeResetDescription
7:4SLEWRATE_OPT_4R/WFh There are four register assignments each storing a slew rate value (chosen out of the 16 available slew rate values). This register bits relate to the 4th option. Go to Programmable Output Slew Rate section for more information.
0h = 0 (fastest)
1h = 1
2h = 2
3h = 3
4h = 4
5h = 5
6h = 6
7h = 7
8h = 8
9h = 9
Ah = 10
Bh = 11
Ch = 12
Dh = 13
Eh = 14
Fh = 15 (slowest)
3:0SLEWRATE_OPT_3R/WAh There are four register assignments each storing a slew rate value (chosen out of the 16 available slew rate values). This register bits relate to the 3rd option. Go to Programmable Output Slew Rate section for more information.
0h = 0 (fastest)
1h = 1
2h = 2
3h = 3
4h = 4
5h = 5
6h = 6
7h = 7
8h = 8
9h = 9
Ah = 10
Bh = 11
Ch = 12
Dh = 13
Eh = 14
Fh = 15 (slowest)

9.4.19 R93 Register (Offset = 5Dh) [Reset = 00h]

R93 is shown in Table 9-97.

Return to the Table 9-77.

Table 9-97 R93 Register Field Descriptions
BitFieldTypeResetDescription
7:1RESERVEDR0h Reserved
0RX_CLKIN0_EN_AC_INPUTR/W0h Enable receiver bias when CLKIN0 is AC coupled
0h = DC Coupled Input
1h = AC Coupled Input

9.4.20 R98 Register (Offset = 62h) [Reset = 00h]

R98 is shown in Table 9-98.

Return to the Table 9-77.

Table 9-98 R98 Register Field Descriptions
BitFieldTypeResetDescription
7:6RESERVEDR0h Reserved
5SLEWRATE_SEL_CLK2_LSBR/W0h LSB CLK2 Slew Rate Control
4SLEWRATE_SEL_CLK3_LSBR/W0h LSB CLK3 Slew Rate Control
3:0RESERVEDR0h Reserved

9.4.21 R99 Register (Offset = 63h) [Reset = 00h]

R99 is shown in Table 9-99.

Return to the Table 9-77.

Table 9-99 R99 Register Field Descriptions
BitFieldTypeResetDescription
7RESERVEDR0h Reserved
6SLEWRATE_SEL_CLK0_LSBR/W0h LSB CLK0 Slew Rate Control
5:3RESERVEDR0h Reserved
2SLEWRATE_SEL_CLK1_LSBR/W0h LSB CLK1 Slew Rate Control
1:0RESERVEDR0h Reserved