SNAS866A December   2023  – September 2024 LMX1214

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Timing Requirements
    7. 5.7 Timing Diagram
    8. 5.8 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
      1. 6.1.1 Range of Dividers
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Power-On Reset
      2. 6.3.2 Temperature Sensor
      3. 6.3.3 Clock Outputs
        1. 6.3.3.1 Clock Output Buffers
        2. 6.3.3.2 Clock MUX
        3. 6.3.3.3 Clock Divider
      4. 6.3.4 AUXCLK Output
        1. 6.3.4.1 AUXCLKOUT Output Format
        2. 6.3.4.2 AUXCLK_DIV_PRE and AUXCLK_DIV Dividers
      5. 6.3.5 SYNC Input Pins
        1. 6.3.5.1 SYNC Pins Common-Mode Voltage
        2. 6.3.5.2 Windowing Feature
    4. 6.4 Device Functional Modes Configurations
      1. 6.4.1 Pin Mode Control
  8. 7 Register Map
    1. 7.1 Device Registers
  9. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 SYNC Input Configuration
      2. 8.1.2 Treatment of Unused Pins
      3. 8.1.3 Current Consumption
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Plots
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Device Support
    2. 9.2 Documentation Support
      1. 9.2.1 Related Documentation
    3. 9.3 Receiving Notification of Documentation Updates
    4. 9.4 Support Resources
    5. 9.5 Trademarks
    6. 9.6 Electrostatic Discharge Caution
    7. 9.7 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information
    1. 11.1 Tape and Reel Information

6.3.4.2 AUXCLK_DIV_PRE and AUXCLK_DIV Dividers

The AUXCLK_DIV_PRE divider and AUXCLK_DIV dividers are used for the AUXCLKOUT output. The AUXCLK_DIV_PRE divider is necessary to divide the frequency down to verify that the input to the AUXCLK_DIV divider is 3.2 GHz or less. When AUXCLK_DIV is not even and not bypassed, the duty cycle is not be 50%. Both the AUXCLKOUT dividers are synchronized by the SYNC feature, which allows synchronization across multiple devices.

Table 6-6 Minimum N-Divider Restrictions
fCLKIN (MHz) AUXCLK_DIV_PRE AUXCLK_DIV TOTAL DIVIDE RANGE
fCLKIN ≤ 3.2 GHz ÷1,2,4 ÷1,2 ,3 ,…1023 [1, 2, ...1023] [2, 4, ... 2046] [4, 8, 4092]
3.2 GHz < fCLKIN≤ 6.4 GHz ÷2,4 ÷1, 2 ,3 ,…1023 [4, ... 2046] [4, 8, 4092]
fCLKIN > 6.4 GHz ÷4 1, 2, 3 ,…1023 [8, 4092]