SNAU260A October   2020  – February 2021 LMK5C33216

ADVANCE INFORMATION  

  1.   Trademarks
  2. 1Introduction
  3. 2EVM Quick Start
  4. 3EVM Configuration
    1. 3.1 Power Supply
    2. 3.2 Logic Inputs and Outputs
    3. 3.3 Switching Between I2C and SPI
    4. 3.4 Generating SYSREF Request
    5. 3.5 XO Input
      1. 3.5.1 38.88-MHz TCXO (Default)
      2. 3.5.2 External Clock Input
    6. 3.6 Reference Clock Inputs
    7. 3.7 Clock Outputs
    8. 3.8 Status Outputs and LEDS
    9. 3.9 Requirements for Making Measurements
  5. 4EVM Schematics
    1. 4.1 Power Supply Schematic
    2. 4.2 Power Distribution Schematic
    3. 4.3 LMK5C33216 and Input Reference Inputs IN0 to IN1 Schematic
    4. 4.4 Clock Outputs OUT0 to OUT3 Schematic
    5. 4.5 Clock Outputs OUT4 to OUT9 Schematic
    6. 4.6 Clock Outputs OUT10 to OUT15 Schematic
    7. 4.7 XO Schematic
    8. 4.8 Logic I/O Interfaces Schematic
    9. 4.9 USB2ANY Schematic
  6. 5EVM Bill of Materials
    1. 5.1 Loop Filter and Vibration Nonsensitive Capacitors
  7. 6Appendix A - TICS Pro LMK5C33216 Software
    1. 6.1 Using the Start Page
      1. 6.1.1 Step 1
      2. 6.1.2 Step 2
      3. 6.1.3 Step 3
      4. 6.1.4 Step 4
      5. 6.1.5 Step 5
      6. 6.1.6 Step 6
      7. 6.1.7 Step 7
    2. 6.2 Using the Status Page
    3. 6.3 Using the Input Page
      1. 6.3.1 Cascaded Configurations
        1. 6.3.1.1 Cascade VCO to APLL Reference
    4. 6.4 Using APLL1, 2, and 3 Pages
    5. 6.5 Using the DPLL1, 2, and 3 Pages
      1. 6.5.1 DPLL DCO
    6. 6.6 Using the Validation Page
    7. 6.7 Using the GPIO Page
    8. 6.8 Using the Outputs Page
  8. 7Revision History

3.5 XO Input

The LMK5C33216 has an XO input (XO_P pin) to accept a reference clock for the Fractional-N APLLs. The XO input determines the output frequency accuracy and stability in free-run or holdover modes. For synchronization applications like SyncE or IEEE 1588, the XO input would typically be driven by a low frequency TCXO, OCXO, or external traceable clock that conforms to the frequency accuracy and holdover stability requirements of the application. For DPLL mode, the XO frequency must have a non-integer frequency relationship with the VCO frequency of any APLLs which utilize XO input as their reference. For APLL only mode (DPLL not used), the XO frequency can have an integer relationship with the VCO to avoid fractional spurs. Any APLL may accept any other APLL as a reference instead of the XO. The BAW on APLL3 provides a good option for a high frequency cascaded referenced.

The XO input of the LMK5C33216 has programmable on-chip input termination and AC-coupled input biasing options to support any clock interface type.

For flexibility, the EVM provides the XO input options (use one at a time). C70 allows an external reference to be provided at SMA connector XO_P (J8). C71 allows one of the on board XO/TCXO/OCXO footprints to be used. By default Y1 is populated with a 38.88 MHz TCXO and selected with the populated R43. Other XO/TCXO/OCXO may be installed and connected using the appropriate resistor. Care should be taken if more than one device is installed to remove resistors for isolation.

GUID-20201017-CA0I-KJMX-FNNK-T25GRFQWMTFK-low.png Figure 3-10 XO Input