The LMK5B33216EVM is an evaluation module for the LMK5B33216 Network Clock Generator and Synchronizer. The EVM can be used for device evaluation, compliance testing, and system prototyping.
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Overview
The LMK5B33216EVM is an evaluation module for the LMK5B33216 Network Clock Generator and Synchronizer. The EVM can be used for device evaluation, compliance testing, and system prototyping. The LMK5B33216 integrates three Analog PLLs (APLL) and three Digital PLLs (DPLL) with programmable loop bandwidth. The EVM includes SMA connectors for clock inputs, optional off-board APLL reference input, and clock outputs to interface the device with 50-Ω test equipment. The onboard TCXO allows the LMK5B33216 to be evaluated in free-running, locked, or holdover mode of operation. The EVM can be configured through the onboard USB microcontroller (MCU) interface using a PC with TI's TICS Pro software graphical user interface (GUI). TICS Pro can be used to program the LMK5B33216 registers.
Features
What is Included
What is Needed
What is Recommended
Figure 1-1 shows the jumper position with red markings. Figure 1-1 shows the DIP switch positions in either green boxes (for ON) or red boxes (for OFF) in the appropriate location.
Table 2-1 describes the default jumper positions for the EVM to power the device from a single 12-V supply provided to VIN4. In positional information about jumpers, “adjacent designator” means the jumper is placed adjacent to the designator. “Opposite designator” means the jumper is placed opposite of the designator.
CATEGORY | REFERENCE DESIGNATOR | POSITION | DESCRIPTION |
---|---|---|---|
Power | JP1 | 1-2 (opposite designator) | LMK5B33216 VDD = 3.3 V from DCDC1 provided by U500 on top of the PCB. |
JP2 | 1-2 (opposite designator) | LMK5B33216 VDDO = 3.3 V from DCDC1 by U500 on top of the PCB. | |
JP4 | 1-2 (opposite designator) | XO VCC = 3.3 V from DCDC1 provided by U500 on top of PCB. | |
Communication | JP5 | 1-2, 3-4 | Connect I2C from onboard USB2ANY to LMK5B33216 |
LMK5B33216 Control Pins | S3 | S3[1:2] = OFF | SCS_ADD = no pullup or pulldown. |
S1, S2, S4 | Sx[1,2] = OFF Sx[3,4] = ON | Enable 3.9k pulldown on GPIO0, GPIO1, and GPIO2 |
To begin using the LMK5B33216, follow the steps below.
Hardware Setup
Verify the EVM default jumper and DIP switch settings shown in Figure 1-1.
Software Setup
Program the LMK5B33216
Measure
Measurements can now be made at the clock outputs.
The LMK5B33216 is a highly-configurable clock chip with multiple power domains, PLL domains, and clock input and output domains. To support a wide range of LMK5B33216 use cases, the EVM was designed with more flexibility and functionality than needed to implement the chip in a customer system application.
This section describes the power, logic, and clock input and output interfaces on the EVM, as well as how to connect, set up, and operate the EVM. Refer to Figure 4-1.
ITEM NO. | REFERENCE DESIGNATORS | DESCRIPTION | |
---|---|---|---|
1 | U1 | LMK5B33216 | |
2 | J500 (VIN4 terminal block header) | External Supply, +12-V DC using default configuration. | |
3 | A | Y1 | Onboard TCXO. Y1 will provide improved holdover stability and allow narrower DPLL loop bandwidths to be used in comparison to the external XO input. |
B | J8 | SMA connector for external XO. To use the external XO, remove the jumper from JP4. | |
4 | J4/5, J6/7 | SMA Ports for Clock Inputs (IN0_P/N and IN1_P/N). IN0_N is not populated and IN0_P is configured for single ended input. IN1 is configured for differential input. | |
5 | J9/11, J10/12, J13/15, J14/16, J17/19, J18/20, J21/J23, J22/24, J25/27, J26/28, J29/31, J30/32, J33/35, J34/36, J37/39, J38/40 | SMA Ports for Clock Outputs | |
6 | S5 | Normally open. Push button for device power down (PDN pin). R76 enables control of the PDN pin through the GUI. R76 is installed by default. | |
7 | JP5 | Jumper header for I2C/SPI interface (MCU to LMK5B33216) | |
8 | D6 | SCL or SCK busy indication LED. | |
9 | J41 | USB Port for MCU |