SNAU270 February   2022 LMK1D1208I

 

  1.   Trademarks
  2. 1 Features
  3. 2 General Description
  4. 3 Signal Path and Control Circuitry
  5. 4 Getting Started
  6. 5 Power Supply Connection
  7. 6 Input Clock
    1. 6.1 Differential Input
    2. 6.2 Single-Ended Input
  8. 7 Output Clock
  9. 8 Using I2C
    1. 8.1 I2C Address Selection
  10. 9 EVM Board Schematic
  11. 10Bill of Materials
  12. 11REACH Compliance

7 Output Clock

The LMK1D1208I generates up to 8 LVDS outputs. Two outputs (OUT0 and OUT4) are available by default on the EVM through the following populated SMAs: J12, J13 (OUT0_P, OUT0_N) and J14, J15 (OUT4_P, OUT4_N).

The LVDS outputs are AC-coupled to their respective SMAs. Each output pair has the 100-Ω termination on the board already populated.

GUID-20211216-SS0I-ZTJZ-XXDN-NTMVKQBTF9CJ-low.png Figure 7-1 Output Clock EVM Layout .