SNAU270 February   2022 LMK1D1208I

 

  1.   Trademarks
  2. 1 Features
  3. 2 General Description
  4. 3 Signal Path and Control Circuitry
  5. 4 Getting Started
  6. 5 Power Supply Connection
  7. 6 Input Clock
    1. 6.1 Differential Input
    2. 6.2 Single-Ended Input
  8. 7 Output Clock
  9. 8 Using I2C
    1. 8.1 I2C Address Selection
  10. 9 EVM Board Schematic
  11. 10Bill of Materials
  12. 11REACH Compliance

6 Input Clock

The LMK1D1208I can receive either a differential or single-ended clock as input. The default board configuration is for an LVDS differential signal at both device inputs. The inputs can be applied through the SMAs: J1, J2 (IN0_P, IN0_N) or J3, J4 (IN1_P, IN1_N). These inputs are AC-coupled to the device. The common-mode voltage is provided by the device on-chip bias generator (VAC_REF pins), which can be measured at TP1 and TP2.

GUID-20211216-SS0I-GGC2-HNZV-47BQMPRZ5DHF-low.pngFigure 6-1 Input Clock Selection Layout.