SNAU271 October   2021 LMK1D1212

 

  1.   Trademarks
  2. 1 Features
  3. 2 General Description
  4. 3 Signal Path and Control Circuitry
  5. 4 Getting Started
  6. 5 Power Supply Connection
  7. 6 Input Clock Selection
    1. 6.1 Differential Input
    2. 6.2 Single-Ended Input
  8. 7 Output Clock
  9. 8 EVM Board Schematic
  10. 9 REACH Compliance
  11. 10Bill of Materials

6 Input Clock Selection

The LMK1D1212 can receive either a differential or single-ended clock as input. The default board configuration is for a differential signal at both device inputs. The inputs can be applied through the SMAs, J3, J4 (IN0_P, IN0_N) or J5, J6 (IN1_P, IN1_N). These inputs are AC-coupled to the device. The common-mode voltage is provided by the device on-chip bias generator (VAC_REF) pins.

LMK1D1212: Jumper, J10, can be used to select between the two input clocks. IN0 is selected when J10 connects IN_SEL to GND. IN1 is selected when J10 connects IN_SEL to VDD.

GUID-20211012-SS0I-JJRM-FTBV-02GDDB6P25RD-low.pngFigure 6-1 Input Clock Selection Layout.