SNAU272 October   2021 LMK1D1216

 

  1.   Trademarks
  2. 1 Features
  3. 2 General Description
  4. 3 Signal Path and Control Circuitry
  5. 4 Getting Started
  6. 5 Power Supply Connection
  7. 6 Input Clock Selection
    1. 6.1 Differential Input
    2. 6.2 Single-Ended Input
  8. 7 Output Clock
  9. 8 EVM Board Schematic
  10. 9 REACH Compliance
  11. 10Bill of Materials

7 Output Clock

The LMK1D1216 generates up to 16 LVDS outputs. Two outputs (OUT0 and OUT8) are available by default on the EVM through the following SMAs: J1, J2 (OUT0_P, OUT0_N) and J5, J6 (OUT8_P, OUT8_N). The LVDS outputs are AC-coupled to their respective SMAs. Each output pair has the 100-Ω termination on the board already populated: R4 (OUT0) and R10 (OUT8).

The LVDS outputs are AC-coupled to their respective SMAs. Each output pair has the 100-Ω termination on the board already populated: R4 (OUT0) and R10 (OUT8).

GUID-20211012-SS0I-CZQT-GZ0F-SWJWDTR1G7VZ-low.png Figure 7-1 Output Clock EVM Layout .