SNAU279A July   2022  – September 2022

 

  1.   Abstract
  2.   Trademarks
  3. 1Introduction
  4. 2EVM Quick Start
  5. 3EVM Configuration
    1. 3.1  Power Supply
    2. 3.2  Logic Inputs and Outputs
    3. 3.3  Switching Between I2C and SPI
    4. 3.4  Generating SYSREF Request
    5. 3.5  XO Input
      1. 3.5.1 48-MHz TCXO (Default)
      2. 3.5.2 External Clock Input
      3. 3.5.3 Additional XO Input Options
      4. 3.5.4 APLL Reference Options
    6. 3.6  Reference Clock Inputs
    7. 3.7  Clock Outputs
    8. 3.8  Status Outputs and LEDs
    9. 3.9  Requirements for Making Measurements
    10. 3.10 Typical Phase Noise Characteristics
  6. 4EVM Schematics
    1. 4.1  Power Supply Schematic
    2. 4.2  Alternative Power Supply Schematic
    3. 4.3  Power Distribution Schematic
    4. 4.4  LMK5B33414 and Input Reference Inputs IN0 to IN1 Schematic
    5. 4.5  Clock Outputs OUT0 to OUT3 Schematic
    6. 4.6  Clock Outputs OUT4 to OUT9 Schematic
    7. 4.7  Clock Outputs OUT10 to OUT13 and Clock Inputs IN2 and IN3 Schematic
    8. 4.8  XO Schematic
    9. 4.9  Logic I/O Interfaces Schematic
    10. 4.10 USB2ANY Schematic
  7. 5EVM Bill of Materials
    1. 5.1 Loop Filter and Vibration Nonsensitive Capacitors
  8. 6Appendix A - TICS Pro LMK5B33414 Software
    1. 6.1  Using the Start Page
      1. 6.1.1 Step 1
      2. 6.1.2 Step 2
      3. 6.1.3 Step 3
      4. 6.1.4 Step 4
      5. 6.1.5 Step 5
      6. 6.1.6 Step 6
      7. 6.1.7 Step 7
    2. 6.2  Using the Status Page
    3. 6.3  Using the Input Page
      1. 6.3.1 Cascaded Configurations
        1. 6.3.1.1 Cascade VCO to APLL Reference
    4. 6.4  Using APLL1, APLL2, and APLL3 Pages
      1. 6.4.1 APLL DCO
    5. 6.5  Using the DPLL1, DPLL2, and DPLL3 Pages
      1. 6.5.1 DPLL DCO
    6. 6.6  Using the Validation Page
    7. 6.7  Using the GPIO Page
    8. 6.8  SYNC/SYSREF/1-PPS Page
    9. 6.9  Using the Outputs Page
    10. 6.10 EEPROM Page
    11. 6.11 Design Report Page
  9. 7Revision History

3 EVM Configuration

The LMK5B33414 is a highly-configurable clock chip with multiple power domains, PLL domains, and clock input and output domains. To support a wide range of LMK5B33414 use cases, the EVM was designed with more flexibility and functionality than needed to implement the chip in a customer system application.

This section describes the power, logic, and clock input and output interfaces on the EVM, as well as how to connect, set up, and operate the EVM. Refer to Figure 4-1.

Table 3-1 Key Components Reference Designators and Descriptions
ITEM NO.REFERENCE

DESIGNATORS

DESCRIPTION
1U1LMK5B33414
2J500 (VIN4 terminal block header)External Supply, +12 V using default configuration.
3AY1

Onboard TCXO. Y1 will provide improved holdover stability and allow narrower DPLL loop bandwidths to be used in comparison to the external XO input.

B

J8

SMA connector for external XO. To use the external XO, remove the jumper from JP4 to power down the on-board TCXO.

4J4/5, J6/7,

J37/J39, J40/J38

SMA Ports for Clock Inputs (IN0_P/N, IN1_P/N, IN2_P/N, and IN3_P/N).

IN0_N is not populated and IN0_P is configured for single ended input. IN1 is configured for a DC-coupled differential input. IN2 and IN3 are configured for an AC-coupled differential input.

5J9/11, J10/12, J13/15, J14/16, J17/19, J18/20, J21/J23, J22/24, J25/27, J26/28, J29/31, J30/32, J33/35, J34/36SMA Ports for Clock Outputs
6S5Normally open. Push button for device power down (PD# pin). R76 enables control of the PD# pin through the GUI. If GUI has PD# unchecked on User Controls page under PINS section, the device will be held in power-down condition no matter state of S5.

R76 is installed by default.

7JP5

Jumper header for I2C/SPI interface (MCU to LMK5B33414)

8D6SCL or SCK busy indication LED.
9J41USB Port for MCU
Figure 3-1 Key Components - EVM Top Side.