SNAU282 September   2022

 

  1.   Abstract
  2.   Trademarks
  3. 1Evaluation Board Kit Contents
  4. 2Quick Start
    1. 2.1 Quick Start Description
      1. 2.1.1 Clock Outputs Page Description
      2. 2.1.2 TICS Pro Tips
  5. 3PLL Loop Filters and Loop Parameters
    1. 3.1 PLL1 Loop Filter
    2. 3.2 PLL2 Loop Filter
  6. 4Default TICS Pro Mode
  7. 5Using TICS Pro to Program the LMK04832-SEP
    1. 5.1 Start TICS Pro Application
    2. 5.2 Select Device
    3. 5.3 Program the Device
    4. 5.4 Restoring a Default Mode
    5. 5.5 Visual Confirmation of Frequency Lock
    6. 5.6 Enable Clock Outputs
  8. 6Evaluation Board Inputs and Outputs
  9. 7Recommended Test Equipment
  10. 8Schematics
  11. 9Bill of Materials
  12.   A USB2ANY Firmware Upgrade
  13.   B TICS Pro Usage
    1. 11.1  Communication Setup
    2. 11.2  User Controls
    3. 11.3  Raw Registers Page
    4. 11.4  Set Modes Page
    5. 11.5  Holdover Page
    6. 11.6  CLKinX Control Page
    7. 11.7  PLL1 and 2 Page
    8. 11.8  SYNC / SYSREF Page
    9. 11.9  Clock Outputs Page
    10. 11.10 Other Page
    11. 11.11 Burst Mode Page

2.1.1 Clock Outputs Page Description

Clock outputs are grouped in pairs. This description applies for all clock outputs on the Clock Outputs page of the TICS Pro GUI (see Section 11.9).

GUID-2D06B156-EF1C-4957-BFB5-D4EEBC7A47AC-low.gifFigure 2-2 Clock Outputs Page Description Diagram.
  1. SYNC_DISX: Prevent the divider from being reset by SYNC/SYSREF path.
  2. DCLKX_Y_DIV: Divide value for the device clock. If set to 1, then DCLKX_Y_DCC (DCC & HS) must = 1.
  3. DDLYdX_EN: Enable dynamic digital delay for this divider.
  4. DCLKX_Y_HSg_PD: If clear, glitchless half-step adjustments are enabled.
  5. DCLKX_Y_HS: Set half step for this divider. DCLKX_Y_DCC (DCC & HS) must = 1.
  6. DCLKX_Y_DDLY_PD: If clear, the digital delay value is assured when a SYNC occurs.
  7. DCLKX_Y_DDLY: The digital delay value to be used when a SYNC occurs.
  8. DCLKX_Y_PD: Power down the device clock divider and path.
  9. DCLKX_Y_DCC: Enable duty cycle correct and half-step for this device clock divider.
  10. DCLKX_Y_POL: If set, polarity of device clock is inverted.
  11. DCLKX_Y_BYP: If set, the device clock divider is bypassed for CLKoutX and #15 must be CML.
  12. CLKoutX_SRC_MUX: Select device clock or SYSREF clock path for CLKoutX.
  13. CLKoutX_Y_IDL: Increase input drive level to improve noise floor at cost of power (approximately 2 mA).
  14. SYSREF_GBL_PD: Set the conditional for SCLKX_Y_DIS_MODE registers.
  15. CLKoutX_FMT: Set the clock output format for CLKoutX.
  16. CLKoutX_Y_ODL: Increase output drive level to improve noise floor at cost of power (approximately 3 mA). No effect for CLKoutX in bypass mode.
  17. CLKoutX_Y_PD: Power down the entire CLKoutX_Y clock pair.
  18. SCLKX_Y_DDLY: The SYSREF clock digital delay setting.
  19. SCLKX_Y_HS: Set half step for the SYSREF output.
  20. SCLKX_Y_ADLY_EN: Enable analog delay for the SYSREF clock path.
  21. SCLKX_Y_ADLY: If enabled, set the analog delay for the SYSREF clock path.
  22. SCLKX_Y_PD: Power down the SYSREF clock path.
  23. SCLKX_Y_POL: If set, polarity of SYSREF output clock is inverted.
  24. CLKoutY_SRC_MUX: Select device clock or SYSREF clock path for CLKoutY.
  25. SCLKX_Y_DIS_MODE: Set the output state of output clock drivers for the SYSREF clock. For values of 1 and 2 works in conjunction with control on this list #14, SYSREF_GBL_PD.
  26. CLKoutY_FMT: Set the clock output format for CLKoutY.
  27. Clock output frequency for CLKoutX and CLKoutY.