SNAU287 November   2023

 

  1.   1
  2.   Description
  3.   Features
  4.   4
  5. 1Evaluation Module Overview
    1. 1.1 Introduction
    2. 1.2 Kit Contents
  6. 2Hardware
    1. 2.1 Evaluation Setup Requirement
    2. 2.2 Configuring the EVM
      1. 2.2.1 Configuring the Power Supply
      2. 2.2.2 Configuring the Control Pins
      3. 2.2.3 Configuring the Clock Outputs
      4. 2.2.4 Using the USB Interface Connection
      5. 2.2.5 EVM Quick Start Guide
    3. 2.3 Modes of Operation
  7. 3Software
    1. 3.1 Using TICS Pro with the LMK3H0102EVM
      1. 3.1.1 Using the LMK3H0102 Wizard
        1. 3.1.1.1 Frequency Plan
        2. 3.1.1.2 Output Formats
        3. 3.1.1.3 Output Enable Pin
        4. 3.1.1.4 OTP Options
        5. 3.1.1.5 Review
        6. 3.1.1.6 Design Report
      2. 3.1.2 Live Debugger
        1. 3.1.2.1 FODs
        2. 3.1.2.2 Outputs
        3. 3.1.2.3 Others
      3. 3.1.3 Programming
        1. 3.1.3.1 Registers
        2. 3.1.3.2 OTP Configuration
      4. 3.1.4 Help
        1. 3.1.4.1 Contact TI
    2. 3.2 Using TI’s USB2ANY Module for In-System Programming of the LMK3H0102
      1. 3.2.1 USB2ANY Board Connections
      2. 3.2.2 Ordering a USB2ANY Module
  8. 4Hardware Design Files
    1. 4.1 Schematics
    2. 4.2 PCB Layout
    3. 4.3 Bill of Materials
  9. 5Additional Information
    1.     Trademarks
  10. 6Related Documentation

2.2.3 Configuring the Clock Outputs

The clock output pairs of the LMK3H0102 are routed via 50-Ω single-ended traces to SMA ports (OUT[1:0]_P/OUT[1:0]_N). These outputs have series resistor (0-Ω populated) options. The default output configuration for the LMK3H0102EVM is AC-coupled LP-HCSL for OUT0 and DC-coupled LP-HCSL for OUT1. Each of these outputs can be configured for AC-LVDS, DC-LVDS, LP-HCSL, and LVCMOS output formats per the Output Format Types section of the LMK3H0102 data sheet.

The REF_CTRL pin of the LMK3H0102 can be configured as an additional LVCMOS clock, REF_CLK, allowing for up to five LVCMOS clock outputs. The REF_CLK output is routed to the REFCLK SMA port through a 33-Ω series resistor, with the option for a 10 pF capacitor to GND.

The output high level of the OUT0 and OUT1 LVCMOS outputs are set by the voltage on the VDDO plane. The output high level of the REF_CLK output is set by the voltage on the VDD plane.