The SYSREF generation circuit includes a SYSREF
pre-divider and post-divider, a pulser with programmable pulse quantity, and a
repeater mode bypass. The SYSREF generator modes re-time the SYSREF signal to the
output clock, verifying the SYSREF output is close to the falling edge of the clock
output with default delay settings. Repeater mode timing is solely determined by the
propagation delay of the device.
To activate the SYSREF generation circuit, the following conditions must be satisfied:
- SYSREFREQ_MODE field must be set
to SYSREF mode.
- SYSREF_MODE field must be set to
the appropriate condition: Continuous, Pulser, or Repeater.
- In generator modes (continuous or
pulser), FINTERPOLATOR % FSYSREF = 0 must be
verified.
- SYSREF_DELAY_BYP field must be
configured appropriately for generator or repeater modes (a GUI autoset
condition normally verifies this whenever SYSREF_MODE is set).
- SYSREFREQ_VCM field must be set
to DC-coupled mode for continuous or pulsed generator output. In repeater mode
output, the SYSREF input can be AC- or DC-coupled and SYSREFREQ_VCM must be set
accordingly.
- For continuous mode, a HIGH
signal must be seen on SYSREFREQ pins continuously. For pulsed generator mode, a
LOW→HIGH transition must be seen on SYSREFREQ pins to trigger the pulser. For
repeater mode, the output follows the input state.