SNAU293 May   2024 LMX1860-SEP

 

  1.   1
  2.   Description
  3.   Features
  4.   Applications
  5.   5
  6. 1Evaluation Module Overview
    1. 1.1 Introduction
    2. 1.2 Kit Contents
    3. 1.3 Specification
    4. 1.4 Device Information
  7. 2Hardware
    1. 2.1 Setup
      1. 2.1.1  Evaluation Setup Requirement
      2. 2.1.2  Connection Diagram
      3. 2.1.3  How to Enable Full SPI Control
      4. 2.1.4  Power Requirements
      5. 2.1.5  Pin Mode Strapping
      6. 2.1.6  Reference Clock
      7. 2.1.7  Output Connections
      8. 2.1.8  Header Information
      9. 2.1.9  Default Configuration
      10. 2.1.10 How to Generate SYSREF
      11. 2.1.11 Multiplier Mode Example
      12. 2.1.12 Divider Mode Example
      13. 2.1.13 Hybrid Mode: SPI and Pin Mode
  8. 3Software
    1. 3.1 Software Installation
    2. 3.2 Software Description
    3. 3.3 USB2ANY Interface
  9. 4Implementation Results
    1. 4.1 Buffer, Divider, and Multiplier Modes
    2. 4.2 SYSREF Generation
    3. 4.3 SYSREF Delay Generators
  10. 5Hardware Design Files
    1. 5.1 Schematic
    2. 5.2 PCB Layout
    3. 5.3 PCB Layer Stack-Up
    4. 5.4 Bill of Materials
  11. 6Additional Information
    1. 6.1 Troubleshooting Guide
      1. 6.1.1 General Guidance
      2. 6.1.2 If Output Is Not Seen on CLKOUT
      3. 6.1.3 If Device Features Are Not Active
      4. 6.1.4 If Multiplier Frequency Is Not Accurate
      5. 6.1.5 If Divider Frequency Is Not Accurate
      6. 6.1.6 If SYSREF Is Not Observed
    2. 6.2 Trademarks

2.1.6 Reference Clock

Connect the CLKINP SMA connector to a high-quality signal source such as an SMA100B signal generator. Both CLKIN inputs are terminated internally with 50Ω to AC-GND (that is, GND connection is formed by an internal capacitor), so no external termination is required or recommended. Input can be driven differentially, connect both CLKINP and CLKINN SMA connectors to a balun or a differential clock source.

The default EVM profile configures the device in buffer mode. LOGICLK is on by default with a predefined output divider value of 128. The input frequency can be modified per the operating range of each functional element if desired. This EVM setup guide and related plots assume 3200MHz input at CLKIN for buffer mode.

To evaluate SYSREF repeater mode, connect the SYSREF input SMAs to a differential output source such as an arbitrary function generator. The EVM connections for the SYSREF input are DC-coupled and provide internal 100Ω termination with several biasing options. At POR, the EVM automatically applies a weak 1.3V common mode bias to the SYSREFREQ pins. However, the default EVM profile configures the SYSREF input for DC-coupled input. In DC-coupled mode, the common mode bias on the SYSREFREQ pins must be between 1V and 2V. The input common mode requirements can be fulfilled with a standard LVDS output buffer.

For evaluating SYNC mode and SYSREF windowing, to have a SYSREFREQ input source capable of consistently meeting setup and hold requirements for a single cycle of the input clock is critical. This can become very challenging at higher frequencies where set up and hold requirements can be < 50ps. Another device capable of picosecond-precision timed pulses, such as LMX2820 or LMX2594, can be used as a reference input to both CLKIN and SYSREF for evaluating these features.