SNAU299 January   2024 LMX1214

 

  1.   1
  2.   Description
  3.   Features
  4.   Applications
  5.   5
  6. 1Evaluation Module Overview
    1. 1.1 Introduction
    2. 1.2 Kit Contents
    3. 1.3 Specification
    4. 1.4 Device Information
  7. 2Hardware
    1. 2.1  Evaluation Setup Requirement
    2. 2.2  Connection Diagram
    3. 2.3  Power Requirements
    4. 2.4  How to Enable Full SPI Control
    5. 2.5  Reference Clock
    6. 2.6  Output Connections
    7. 2.7  Switch Information
    8. 2.8  Default Configuration
    9. 2.9  Divider Mode Example
    10. 2.10 Hybrid Mode: SPI and Pin Mode
  8. 3Software
    1. 3.1 Software Installation
    2. 3.2 Software Description
    3. 3.3 USB2ANY Interface
  9. 4Implementation Results
    1. 4.1 Evaluation Setup
      1. 4.1.1 Buffer and Divider Mode
  10. 5Hardware Design Files
    1. 5.1 Schematic
    2. 5.2 PCB Layout
      1. 5.2.1 PCB Layer Stack-Up
    3. 5.3 Bill of Materials
  11. 6Additional Information
    1. 6.1 Troubleshooting Guide
      1. 6.1.1 General Guidance
      2. 6.1.2 If Output Is Not Seen on CLKOUT
      3. 6.1.3 If Device Features Are Not Active
      4. 6.1.4 If Divider Frequency Is Not Accurate
    2. 6.2 Trademarks

4.1.1 Buffer and Divider Mode

From the top-menu, click Default Configuration. This automatically loads the buffer mode profile.

GUID-20240122-SS0I-1VLT-GZ9D-CCWQTFVP7VMB-low.svg Figure 4-1 Loading the Default Configuration

If termination is not applied on all output pins, then manually disable the unused outputs using the CLKOUTx_EN/AUXCLKOUT_EN fields. Powering down unused channels greatly reduces current consumption and for the logic clocks in particular can reduce spurious interference.

After the profile is loaded and any changes required have been made, the signal analyzer has an 3200MHz signal at around +6-dBm single-ended, or +9-dBm differential.

GUID-20240122-SS0I-B4VM-QHWR-N2GNVTKFJX5R-low.png Figure 4-2 3200MHz Buffer Mode Signal Analyzer Plot

To activate divider mode, change the CLK_MUX field to specify divider and change the CLK_DIV field to specify the frequency scaling factor. To make sure the device enters each mode cleanly, the desired configuration must be prepared in the GUI. Then, from the User Controls page, reset the device by toggling the RESET field. Finally, the registers must be reloaded using the USB Communications → Write All Registers menu option, or by pressing the accelerator keys, CTRL + L.

GUID-20240122-SS0I-SDQN-SK2V-RDQJWTC3SBD2-low.png Figure 4-3 3200MHz Divide by 2 Mode Signal Analyzer Plot