SNAU299 January   2024 LMX1214

 

  1.   1
  2.   Description
  3.   Features
  4.   Applications
  5.   5
  6. 1Evaluation Module Overview
    1. 1.1 Introduction
    2. 1.2 Kit Contents
    3. 1.3 Specification
    4. 1.4 Device Information
  7. 2Hardware
    1. 2.1  Evaluation Setup Requirement
    2. 2.2  Connection Diagram
    3. 2.3  Power Requirements
    4. 2.4  How to Enable Full SPI Control
    5. 2.5  Reference Clock
    6. 2.6  Output Connections
    7. 2.7  Switch Information
    8. 2.8  Default Configuration
    9. 2.9  Divider Mode Example
    10. 2.10 Hybrid Mode: SPI and Pin Mode
  8. 3Software
    1. 3.1 Software Installation
    2. 3.2 Software Description
    3. 3.3 USB2ANY Interface
  9. 4Implementation Results
    1. 4.1 Evaluation Setup
      1. 4.1.1 Buffer and Divider Mode
  10. 5Hardware Design Files
    1. 5.1 Schematic
    2. 5.2 PCB Layout
      1. 5.2.1 PCB Layer Stack-Up
    3. 5.3 Bill of Materials
  11. 6Additional Information
    1. 6.1 Troubleshooting Guide
      1. 6.1.1 General Guidance
      2. 6.1.2 If Output Is Not Seen on CLKOUT
      3. 6.1.3 If Device Features Are Not Active
      4. 6.1.4 If Divider Frequency Is Not Accurate
    2. 6.2 Trademarks

Device Information

The high-frequency capability and extremely low jitter of this device makes a great design to clock precision, high-frequency data converters without degradation to the signal-to-noise ratio. LMX1214 contains four high-frequency clock outputs and an additional AUXCLK output with a larger divider range than all clock outputs. Having the jitter of the clock be less than the aperture jitter of the data converter is critical. In applications where more than four data converters must be clocked, a variety of cascading architectures can be developed using multiple devices to distribute all the high-frequency clocks required. With low jitter and noise floor, this device combined with an ultra-low noise reference clock source is an exemplary design for clocking data converters, especially when sampling above 3GHz.