SNAU307A May   2024  – May 2024 LMKDB1204

 

  1.   1
  2.   Description
  3.   Features
  4.   Applications
  5.   5
  6. Evaluation Module Overview
    1. 1.1 Introduction
    2. 1.2 Kit Contents
    3. 1.3 Specification
    4. 1.4 Device Information
  7. EVM Quick Start
    1. 2.1 Hardware Setup
    2. 2.2 Software Setup
      1. 2.2.1 TICS Pro GUI Setup
      2. 2.2.2 Power Up Sequence
    3. 2.3 EVM Measurements
  8. Hardware
    1. 3.1 Device Operation Modes
    2. 3.2 EVM Configuration
      1. 3.2.1 Power Supply
      2. 3.2.2 Logic Input and Outputs
      3. 3.2.3 Clock Input
      4. 3.2.4 Clock Outputs
      5. 3.2.5 Status Outputs, LEDs, and Test Points
  9. Software
    1. 4.1 TICS Pro LMKDB1204 Software
      1. 4.1.1 Input
        1. 4.1.1.1 Input Selection (CLKIN_SEL Register)
        2. 4.1.1.2 Input Interface Type
        3. 4.1.1.3 Input Termination
        4. 4.1.1.4 Auto Output Disable (AOD)
        5. 4.1.1.5 LOS Event
        6. 4.1.1.6 LOS Readback
      2. 4.1.2 Device Info and EVM Setup
        1. 4.1.2.1 Device Info
        2. 4.1.2.2 EVM Setup
        3. 4.1.2.3 SMBus
      3. 4.1.3 Output
        1. 4.1.3.1 SMBus
          1. 4.1.3.1.1 Output Slew Rate Control
        2. 4.1.3.2 OE and ZOUT_SEL Pin Control
  10. Implementation Results
    1. 5.1 Typical Phase Noise Characteristic
  11. Hardware Design Files
    1. 6.1 Schematics
    2. 6.2 PCB Layouts
    3. 6.3 Bill of Materials (BOM)
  12. Compliance Information
    1. 7.1 Compliance and Certifications
  13. Additional Information
    1. 8.1 Trademarks
  14. References
  15. 10Revision History

Clock Outputs

LMKDB1204 has four differential clock outputs (CLK[0:3]_P/N). All the outputs are DC coupled with a capacitive load of 2pF.

WARNING: DC-coupled clocks must not be directly connected to RF equipment which cannot accept DC voltages greater than 0V, such as spectrum analyzers and phase noise analyzers.
Table 3-9 ZOUT_SEL
ZOUT_SEL OUTPUT LEVEL OUTPUT IMPEDANCE
Low (default) 85Ω output impedance
High 100Ω output impedance