SNLA132G October 2011 – November 2020 DS90UB928Q-Q1 , DS90UB941AS-Q1 , DS90UB948-Q1 , DS90UH925Q-Q1 , DS90UH926Q-Q1 , DS90UH940N-Q1
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The Texas Instruments' FPD-Link III family of products (Table 1-1) offers an internal test pattern generator. This feature provides a user-friendly method for quickly debugging and testing both integrated displays, as well as the link between the serializer and deserializer. This app note focuses specifically on FPD Link III IVI (In Vehicle Infotainment) devices for display applications (94x and 92x).
Serializers | Deserializers |
---|---|
DS90UH925Q-Q1/DS90UB925Q-Q1 | DS90UH926Q-Q1/DS90UB926Q-Q1 |
DS90UB921-Q1 | DS90UB924-Q1 |
DS90UH927Q-Q1/DS90UH927Q-Q1 | DS90UH928Q-Q1/DS90UB928Q-Q1 |
DS90UH947-Q1/DS90UH947-Q1 | DS90UH948-Q1/DS90UB948-Q1 |
DS90UH929-Q1/DS90UB929-Q1 | DS90UH940-Q1/DS90UB940-Q1 |
DS90UH949-Q1/DS90UB949-Q1 | DS90UH940N-Q1/DS90UB940N-Q1 |
DS90UH949A-Q1/DS90UB949A-Q1 | |
DS90UH941AS-Q1/DS90UB941AS-Q1 |
The internal test patterns are simple and repetitive in order to allow quick visual verification of system and display panel operation. As long as the device is not in power down mode, a test pattern can be generated, even if the device is not linked to a source. If no clock is received, the test pattern can be configured to use an internally generated programmable pixel clock.
Video timing may be based on external control signals (HS, VS, DE) provided at the serializer inputs, or they may be generated internally by either the serializer or the deserializer (Figure 2-1).
No pin configuration is required to enable or control the pattern generation feature. All aspects of pattern generation are controlled through the device control registers, accessible locally through the device I2C interface, or remotely via the FPD-Link III bidirectional control channel. The test pattern generation feature is able to handle a wide range of display timings and test image options: