SNLA132G October   2011  – November 2020 DS90UB928Q-Q1 , DS90UB941AS-Q1 , DS90UB948-Q1 , DS90UH925Q-Q1 , DS90UH926Q-Q1 , DS90UH940N-Q1

 

  1.   Trademarks
  2. 1Introduction
  3. 2Overview of Internal Test Pattern Generation
    1. 2.1 Color Mode
    2. 2.2 Video Timing Modes
    3. 2.3 Clock Generation
    4. 2.4 Pattern Selection
    5. 2.5 Pattern Inversion
    6. 2.6 Auto-Scrolling
  4. 3Serial Control Bus Registers for Internal Test Pattern Generation
    1. 3.1 Direct Register Map
      1. 3.1.1 Control and Configuration
      2. 3.1.2 Indirect Access Address and Data
      3. 3.1.3 DS90Ux928Q-Q1/DS90UB924-Q1 Internal Clock Source
    2. 3.2 Indirect Register Map
      1. 3.2.1 General Control
      2. 3.2.2 Internal Timing Control
      3. 3.2.3 Auto-Scrolling Control
  5. 4Configuration Examples
    1. 4.1 Auto-Scrolling Configuration
    2. 4.2 Internal Default Timing Configuration
    3. 4.3 Custom Display Configuration
    4. 4.4 1080p60 with External Clock Example Configuration
    5. 4.5 Resolution Readback Example
  6. 5Conclusion
  7. 6References
  8. 7Revision History

4.3 Custom Display Configuration

This example configures the pattern generator for a custom resolution with the pixel clock and all timing signals generated internally:

Table 4-1 Custom Display Example
ParameterValueUnits
Pixel Clock37.007MHz
Total Horizontal Width1176pixels
Total Vertical Height525pixels
Active Horizontal Width800pixels
Active Vertical Height480pixels
Horizontal Sync Width10pixels
Vertical Sync Width2pixels
Horizontal Back Porch216pixels
Vertical Back Porch35pixels
Horizontal Sync PolarityNegative-
Vertical Sync PolarityNegative-

Configuration Sequence

  1. Set Pixel Clock and Active Frame Size. Active H Width: 800 (dec) = 0011 0010 0000 (bin), Active V Height: 480 (dec) -> 0001 1110 0000 (bin)
    1. Write 0x03 (Table 3-2) to address 0x66 PGIA (Table 3-2) to enable PGCDC1, then write 0x06 (Table 3-9) to address 0x67 PGID (Table 3-2) to set the clock divider to be 6 (200/33.3).
    2. Write 0x07 (Table 3-2) to address 0x66 PGIA (Table 3-2) to enable PGAFS1, then write 0x20 (Table 3-13) to address 0x67 PGID (Table 3-2) to set desired Active Horizontal Width.
    3. Write 0x08 (Table 3-2) to address 0x66 PGIA (Table 3-2) to enable PGAFS2, then write 0x03 (Table 3-14) to address 0x67 PGID (Table 3-2) to set desired Active Vertical and Horizontal Widths.
    4. Write 0x09 (Table 3-2) to address 0x66 PGIA (Table 3-2) to enable PGAFS3, then write 0x1E (Table 3-15) to address 0x67 PGID (Table 3-2) to set desired Active Vertical Width.
    Note:

    33.3 MHz (200/6) is the closest available frequency to the desired 37.007 MHz. 200 MHz clock can be anywhere from 140 MHz to 260 MHz, so the generated pixel clock can be between 23.3 MHz and 43.3 MHz, with a nominal value of 33.3 MHz. Therefore, the internal timing with an external, more accurate pixel clock is allowed by setting 0x65 bit 3 (Table 3-1).

  2. Set Total Frame Size. Total H Width: 1176 (dec) -> 0100 1001 1000 (bin), Total V Width: 525 (dec) -> 0010 0000 1101 (bin)
    1. Write 0x04 (Table 3-2) to address 0x66 PGIA (Table 3-2) to enable PGTFS1, then write 0x98 (Table 3-10) to 0x67 PGID (Table 3-2) to set desired Total Horizontal Width.
    2. Write 0x05 (Table 3-2) to address 0x66 PGIA (Table 3-2) to enable PGTFS2, then write 0xD4 (Table 3-14) to address 0x67 PGID (Table 3-2) to set desired Total Vertical and Horizontal Widths.
    3. Write 0x06 (Table 3-2) to address 0x66 PGIA (Table 3-2) to enable PGTFS3, then write 0x20 (Table 3-12) to address 0x67 PGID (Table 3-2) to set desired Total Vertical Width.
  3. Set Back Porch. H Back Porch: 216 (dec) CLK (effective from 217th CLK -> 1101 1000 (bin), V Back Porch: 35 (dec) lines (effective from 36th line -> 0010 0011 (bin)
    1. Write 0x0C (Table 3-2) to address 0x66 PGIA (Table 3-2) to enable PGHBP, then write 0xD8 (Table 3-18) to address 0x67 PGID (Table 3-2) to set desired Horizontal Back Porch Width.
    2. Write 0x0D (Table 3-2) to address 0x66 PGIA (Table 3-2) to enable PGVBP, then write 0x23 (Table 3-19) to address 0x67 PGID (Table 3-2) to set desired Vertical Back Porch Width.
  4. Set Sync Widths. H Sync Width: 10 (dec) pixels 1010 (bin), V Sync Width: 2 (dec) lines 0010 (bin)
    1. Write 0x0A (Table 3-2) to address 0x66 PGIA (Table 3-2) to enable PGHSW, then write 0x0A (Table 3-18) to address 0x67 PGID (Table 3-2) to set desired Horizontal Sync Width.
    2. Write 0x0B (Table 3-2) to address 0x66 PGIA (Table 3-2) to enable PGVSW, then write 0x02 (Table 3-19) to address 0x67 PGID (Table 3-2) to set desired Vertical Sync Width.
  5. Set Sync Polarities.
    1. Write 0x0E (Table 3-2) to address 0x66 PGIA (Table 3-2) to enable PBSC, then write 0x03 (Table 3-18) to address 0x67 PGID (Table 3-2) to set desired horizontal and vertical sync widths to "Negative".
  6. Enable Pattern Generation
    1. Write 0x03 to address 0x65 PGCFG (Table 3-2) to enable 24-bit with internal Clock.
    2. (DS90Ux928Q-Q1 and DS90UB924-Q1 only) Write 0x02 to address 0x39 (PG INT CLK) to enable Pattern Generator Internal Clock
    3. Write 0x11 to address 0x64 PGCTL (Table 3-2) enable Pattern Generator with White pattern or 1 of 14 patterns that provided.