SNLA224A June   2014  – January 2024 DS90UB913A-Q1 , DS90UB954-Q1 , DS90UB960-Q1

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Introduction
  5. 2Theory of Operation for Power Over Coax
    1. 2.1 Inductor Characteristics
    2. 2.2 Capacitor Characteristics
    3. 2.3 Ferrite Bead Characteristics
  6. 3Design Considerations
    1. 3.1 Frequency Range
    2. 3.2 Power Considerations
    3. 3.3 Inductor Size Considerations
    4. 3.4 Layout Considerations
  7. 4FPD-Link PoC Requirements
    1. 4.1 Channel Requirements
    2. 4.2 PoC Noise Requirements
      1. 4.2.1 VPoC Noise and Pulse
      2. 4.2.2 RIN+ Noise
      3. 4.2.3 Causes of PoC Noise
      4. 4.2.4 Noise Measurement Best Practices
      5. 4.2.5 Reducing Effects of PoC Noise
  8. 5TI Recommended PoC Networks
    1. 5.1 PoC Network From FPD-Link III Data Sheet
    2. 5.2 Murata Networks
      1. 5.2.1 Murata Network 1
      2. 5.2.2 Murata Network 2
      3. 5.2.3 Murata Network 3
    3. 5.3 TDK Networks
      1. 5.3.1 TDK Network 1
      2. 5.3.2 TDK Network 2
      3. 5.3.3 TDK Network 3
      4. 5.3.4 TDK Network 4
      5. 5.3.5 TDK Network 5
      6. 5.3.6 TDK Network 6
      7. 5.3.7 TDK Network 7
      8. 5.3.8 TDK Network 8
    4. 5.4 Coilcraft Networks
      1. 5.4.1 Coilcraft Network 1
      2. 5.4.2 Coilcraft Network 2
      3. 5.4.3 Coilcraft Network 3
      4. 5.4.4 Coilcraft Network 4
  9. 6Summary
  10. 7References
  11. 8Revision History

3.1 Frequency Range

To design an appropriate PoC network, consider the frequency range that the network must be able to filter. The operational frequency range of FPD-Link communication depends on the particular device pairing and mode configuration.

For example, a system using the DS90UB953-Q1 and DS90UB954-Q1 running in synchronous mode with a reference clock of 26 MHz will operate with a forward channel rate of 4.16 Gbps (up to 2.1 GHz) and a back channel of 50 Mbps (down to 25 MHz). So the chosen PoC network needs to support a frequency range of 25 MHz to 2.1 GHz. However, the same devices running in non-synchronous external clock mode with a reference clock of 26 MHz will operate with a forward channel rate of 2.08 Gbps (up to 1.04 GHz) and a back channel of 10 Mbps (down to 5 MHz). For this configuration, the chosen PoC network needs to support a frequency range of 5 MHz to 1.04 GHz. Understanding the operational frequency is particularly important for designs that may potentially support multiple configurations.

Table 4-2 shows some common SerDes configurations and their forward and back channel communication frequencies. The last column shows the frequency range that the PoC network must be able to filter. For additional details on device compatibility and mode configurations, please refer to the respective device data sheets.

Table 3-1 PoC Frequency Ranges
Serializer Deserializer Mode Clock BC Frequency FC Frequency PoC Filter Frequency Range
DS90UB913A-Q1 DS90UB914-Q1 12 Bit LF 50 MHz 2.5 MHz 700 MHz 1.25 MHz - 700 MHz
DS90UB933-Q1 DS90UB934-Q1 12 Bit 100 MHz 2.5 MHz 935 MHz 1.25 MHz - 935 MHz
DS90UB933-Q1 DS90UB954-Q1 10 Bit 100 MHz 2.5 MHz 700 MHZ 1.25 MHz - 700 MHZ
DS90UB953-Q1 DS90UB934-Q1 DVP 25 MHz 2.5 MHz 350 MHZ 1.25 MHz - 350 MHZ
DS90UB954-Q1 Synchronous 26 MHz 50 MHz 2.1 GHZ 25 MHz - 2.1 GHZ
DS90UB954-Q1 Non-Synchronous 52 MHz 10 MHz 2.1 GHz 5 MHz - 2.1 GHz