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The DP83867 is a robust, low power, fully featured Physical Layer transceiver with integrated PMD sublayers to support the 10BASE-Te, 100BASE-TX, and 1000BASE-T Ethernet protocols.
Figure 1-1 is a high-level system block diagram of a typical DP83867 application.
The DP83867 can connect to an Ethernet MAC and to a media. The connection to the media is via a transformer and a connector.
DP83867 Version | MAC interface | Pin number/ package |
---|---|---|
DP83867IR/CR | RGMII | 48 pins / QFN package |
DP83867IS/CS/DP83867E | SGMII | 48 pins/ QFNpackage |
DP83867IRPAPR | MII/GMII/RGMII | 64 pins / QFP package |
The following sections approach the debug from a high level, attempting to start with application characteristics that have a broad impact and then zeroing in on more focused aspects of the design.
Read the registers and verify the default values shown in the data sheet. Note that the initial values of some registers can vary based on strap options.
The expected register values for PHY operation and link in 1000 Mbps with auto-negotiation enabled are shown in Table 2-1.
Register Address (h) | Register Value (h) | Comments |
---|---|---|
0x0000 | 0x1140 |
MII loopback; Auto-negotiation enable and disable |
0x0001 | 0x769D | Link Status |
0x0003 | 0xA231 | PHY revision |
0x0004 (1) | 0x0061 | DUT 10/100Mbps advertisement |
0x0005 (2) | 0xC1E1 | LP 10/100Mbps advertisement |
0x0009 | 0x0300 |
Compliance test mode; DUT 1000Base speed advertisement |
0x000A | 0x3C00 | LP 1000Base speed advertisement |
0x0010 | 0x5048 |
Enable SGMII; Enable Power-Saving Mode; Manual MDI or MDIX configuration |
0x0011 | 0xBF02 | PHY Status |
0x0012 | 0x0000 | Interrupt status |
0x0013 | 0x1C42 | Interrupt status 2 |
0x0014 | 0x29C7 | Enable Speed optimization |
0x0015 | 0x0000 | RX_ER counter |
0x0016 | 0x0000 | Enable PRBS generator and checker; Enable Loopback |
0x0017 | 0x0040 |
PRBS status |
0x0018 | 0x6150 |
LED configuration |
0x0019 | 0x4444 |
LED configuration 2 |
0x001E | 0x0002 | TDR register; Enable Auto-MDIX |
0x006E (3) | Based on strap resistors | Strap status register |
0x006F (3) | Based on strap resistors | Strap status register2 |
With the PHY linked in a given speed, use these values as a reference to identify any variance from the expected operation.
Example: After powering and linking the PHY in 10 Mbps, register 0x0001 is read at hex value 7969. Noting the difference in this value from the expected value of 796D, the equivalent binary values are used to identify which bits are distinct. In this case, bit[2] is low, while the expected value is high. Referencing the data sheet register map, bit[2] of register 0x0001 corresponds to link status. From this, it is known that the PHY is not linked.
Repeating this process for any values distinct from the expected values shown in Table 2-1 help diagnose the exact state of the PHY for any encountered issues.
For information about reading and writing registers using the USB-2-MDIO interface, refer to the Section 3.8.
Reference and verify all of the noted schematic and layout recommendations in the following spreadsheet: