SNLA246C October   2015  – April 2024 DP83867CR , DP83867CS , DP83867E , DP83867IR , DP83867IS

 

  1.   1
  2.   Trademarks
  3. 1Introduction
  4. 2Troubleshooting the Application
    1. 2.1 Read and Check Register Values for Basic Health Check
    2. 2.2 Schematic and Layout Checklist
    3. 2.3 Component Checklist
      1. 2.3.1 Magnetics
      2. 2.3.2 Crystal / Oscillator
    4. 2.4 Peripheral Pin Checks
      1. 2.4.1 Power Supplies
      2. 2.4.2 RBIAS Voltage and Resistance
      3. 2.4.3 Probe the XI Clock
      4. 2.4.4 Probe the RESET_N Signal
      5. 2.4.5 Probe the Strap Pins During Initialization
      6. 2.4.6 Probe the Serial Management Interface Signals (MDC, MDIO)
      7. 2.4.7 Probe the MDI Signals
    5. 2.5 Link Quality Check
    6. 2.6 Built-in Self Test With Various Loopback Modes
    7. 2.7 Debugging MAC Interface
      1. 2.7.1 RGMII Debug
      2. 2.7.2 SGMII Debug
  5. 3Application Specific Debugs
    1. 3.1 Improving Link-up Margins for Short Cables
    2. 3.2 Improving Link Margins across Different Channels
    3. 3.3 Link up in 100Mbps Full Duplex Force Mode
    4. 3.4 Unstable Link Up Debug in 1Gbps communication
    5. 3.5 DP83867PHY and DP83867PHY Cannot Link Up in 1Gbps
    6. 3.6 Compliance Debug
    7. 3.7 EMC Debug
    8. 3.8 Tools and References
      1. 3.8.1 DP83867 Register Access
      2. 3.8.2 Extended Register Access
  6. 4Conclusion
  7. 5References
  8. 6Revision History

2.1 Read and Check Register Values for Basic Health Check

Read the registers and verify the default values shown in the data sheet. Note that the initial values of some registers can vary based on strap options.

The expected register values for PHY operation and link in 1000 Mbps with auto-negotiation enabled are shown in Table 2-1.

Table 2-1 DP83867 Register Value References
Register Address (h) Register Value (h) Comments
0x0000 0x1140

MII loopback;

Auto-negotiation enable and disable
0x0001 0x769D Link Status
0x0003 0xA231 PHY revision
0x0004 (1) 0x0061 DUT 10/100Mbps advertisement
0x0005 (2) 0xC1E1 LP 10/100Mbps advertisement
0x0009 0x0300

Compliance test mode;

DUT 1000Base speed advertisement
0x000A 0x3C00 LP 1000Base speed advertisement
0x0010 0x5048

Enable SGMII;

Enable Power-Saving Mode;

Manual MDI or MDIX configuration
0x0011 0xBF02 PHY Status
0x0012 0x0000 Interrupt status
0x0013 0x1C42 Interrupt status 2
0x0014 0x29C7 Enable Speed optimization
0x0015 0x0000 RX_ER counter
0x0016 0x0000 Enable PRBS generator and checker;

Enable Loopback
0x0017 0x0040

PRBS status
0x0018 0x6150

LED configuration
0x0019 0x4444

LED configuration 2
0x001E 0x0002 TDR register;

Enable Auto-MDIX
0x006E (3) Based on strap resistors Strap status register
0x006F (3) Based on strap resistors Strap status register2

With the PHY linked in a given speed, use these values as a reference to identify any variance from the expected operation.

(1) Enable only 1000 Mbps could be perform by disabling advertisements of other speeds in register 0x4 (10Mbps and 100Mbps).
(2) The value of register 0x5 will vary depending on link partner advertisements.
(3) 0x006E and 0x006F are extended registers

Example: After powering and linking the PHY in 10 Mbps, register 0x0001 is read at hex value 7969. Noting the difference in this value from the expected value of 796D, the equivalent binary values are used to identify which bits are distinct. In this case, bit[2] is low, while the expected value is high. Referencing the data sheet register map, bit[2] of register 0x0001 corresponds to link status. From this, it is known that the PHY is not linked.

Repeating this process for any values distinct from the expected values shown in Table 2-1 help diagnose the exact state of the PHY for any encountered issues.

For information about reading and writing registers using the USB-2-MDIO interface, refer to the Section 3.8.