SNLA246C October 2015 – April 2024 DP83867CR , DP83867CS , DP83867E , DP83867IR , DP83867IS
The DP83867 uses an AGC gain convergence circuit (automatic gain control of MDI receiver) to provide faster linkup. There is a tradeoff between the linkup time and gain mismatch between pairs. In applications where packet errors are observed, gain matching can be improved for more optimal link by increasing the gain convergence time with the following register writes:
begin
// Hard reset
001F 8000
// Increase time for AGC
0102 7477
// No AGC Re-train
00E4 0080
// Soft reset
001F 4000
end