SNLA246C October   2015  – April 2024 DP83867CR , DP83867CS , DP83867E , DP83867IR , DP83867IS

 

  1.   1
  2.   Trademarks
  3. 1Introduction
  4. 2Troubleshooting the Application
    1. 2.1 Read and Check Register Values for Basic Health Check
    2. 2.2 Schematic and Layout Checklist
    3. 2.3 Component Checklist
      1. 2.3.1 Magnetics
      2. 2.3.2 Crystal / Oscillator
    4. 2.4 Peripheral Pin Checks
      1. 2.4.1 Power Supplies
      2. 2.4.2 RBIAS Voltage and Resistance
      3. 2.4.3 Probe the XI Clock
      4. 2.4.4 Probe the RESET_N Signal
      5. 2.4.5 Probe the Strap Pins During Initialization
      6. 2.4.6 Probe the Serial Management Interface Signals (MDC, MDIO)
      7. 2.4.7 Probe the MDI Signals
    5. 2.5 Link Quality Check
    6. 2.6 Built-in Self Test With Various Loopback Modes
    7. 2.7 Debugging MAC Interface
      1. 2.7.1 RGMII Debug
      2. 2.7.2 SGMII Debug
  5. 3Application Specific Debugs
    1. 3.1 Improving Link-up Margins for Short Cables
    2. 3.2 Improving Link Margins across Different Channels
    3. 3.3 Link up in 100Mbps Full Duplex Force Mode
    4. 3.4 Unstable Link Up Debug in 1Gbps communication
    5. 3.5 DP83867PHY and DP83867PHY Cannot Link Up in 1Gbps
    6. 3.6 Compliance Debug
    7. 3.7 EMC Debug
    8. 3.8 Tools and References
      1. 3.8.1 DP83867 Register Access
      2. 3.8.2 Extended Register Access
  6. 4Conclusion
  7. 5References
  8. 6Revision History

3.5 DP83867PHY and DP83867PHY Cannot Link Up in 1Gbps

If two DP83867PHYs are able to link up at 10Mbps and 100Mbps but not able to link up at 1Gbps, please refer to the following debug process:

Note: This errata only occur in old revision of the DP83867PHY (Register 0x0003 = A0F1)
  • Try software reset by writing register 0x001F = 4000 on one of the DP83867PHY and see if that resolve the issue.
  • Read register 0x0005[15] and If 0x0005 bit[15] = 0,
    • Auto-MDIX is most likely not complete. Both of the PHY is sending Auto-MDIX FLP_Brust in the same channel at the same time and result in deadlock situation.

    Solution:

    • Change Auto MDIX timer on one of the PHY can prevent the deadlock situation.
    • Change register 0x002C bit[32] = 0 on one of the DP83867PHY
      GUID-C38F3DE5-BECD-4069-8577-BECAB51DAECC-low.png
    • write 0x001F to 4000 to software reset the PHY
  • Read register 0x0005[15] and If 0x0005 bit[15] = 1
    • Auto-MDIX is complete and Auto-negotiation pseudo random number (PRN) is most likely be the issue. Pseudo random number (PRN) sending random number to determine which PHY is Master PHY (clocked from a local source) and which one is the slave PHY (clocked from the recovered clock on the received data stream) when both PHY are communicate in 1000Base-T. This can be check through register 0x000A bit[14].
    • However, the PRN is not exactly random and if both DP83867 start auto-negotiation at the same time, there is a possibility both DP83867 send out the exact same random seed (PRN) and result in dead lock.

    Solution:

    • Write 0x0009 bit[12:11] to 11 on one of the DP83867PHY and write 0x0009 bit[12 :11] to 10 on another DP83867PHY. This register can force one of the PHY to always be MASTER in 1000Base-T communication to prevent the Pseudo random number (PRN) process.
    • Write 0x001F to 4000 to software reset the PHY or write 0x0000[9] =1 to restart the auto-negotiation