6.4 Critical Signal Routing

Circuit board layout and stack-up for the FPD-Link III devices should be designed to provide a low-noise power feed to the device. It is also good layout practice to separate high-frequency or high-level inputs and outputs to minimize unwanted stray noise pickup, feedback, and interference.

The engineer can use thin dielectrics (2 to 4 mils) for power or ground sandwiches to improve power system performance. This arrangement provides plane capacitance for the PCB power system with low-inductance parasitics, which has proven to be especially effective at high frequencies, and makes the value and placement of external bypass capacitors less critical.

Some devices provide separate power and ground pins for different portions of the circuit. This is done to isolate switching noise effects between different sections of the circuit. Separate planes on the PCB are typically not required.

Pin Description tables typically provide guidance on which circuit blocks are connected to which power pin pairs. In some cases, an external filter may be used to provide clean power to sensitive circuits, such as PLLs. Use a four-layer board minimum with a power and ground plane.

Place the LVCMOS signals away from the differential lines to prevent coupling from the LVCMOS lines to the differential lines. Differential impedance of 100 Ω are typically recommended for STP interconnect and single-ended impedance of 50 Ω for coax interconnect. The closely coupled lines can help ensure that coupled noise will appear as common-mode, and thus is rejected by the receivers. The tightly coupled lines will also radiate less.