SNLA308A April   2019  – October 2020 DS90UB941AS-Q1 , DS90UH941AS-Q1

 

  1.   Trademarks
  2. 1 Introduction
  3. 2 Superframe Requirements
    1. 2.1 Left/Right 3D Format
    2. 2.2 Alternate Line 3D Format
    3. 2.3 Alternate Pixel 3D Format
  4. 3 Video Processing Status Monitoring
    1. 3.1 VIDEO_3D_STS Register (Address = 58h) [reset = 0h]
  5. 4 Superframe Splitting
  6. 5 Frame Cropping
    1. 5.1 Cropping Control Registers
      1. 5.1.1 CROP_START_X0_CROP_START_X0_P1 Register (Address = 36h) [reset = 0h]
      2. 5.1.2 CROP_START_X1_CROP_START_X1_P1 Register (Address = 37h) [reset = 0h]
      3. 5.1.3 CROP_STOP_X0_CROP_STOP_X0_P1 Register (Address = 38h) [reset = 0h]
      4. 5.1.4 CROP_STOP_X1_CROP_STOP_X1_P1 Register (Address = 39h) [reset = 0h]
      5. 5.1.5 CROP_START_Y0_CROP_START_Y0_P1 Register (Address = 3Ah) [reset = 0h]
      6. 5.1.6 CROP_START_Y1_CROP_START_Y1_P1 Register (Address = 3Bh) [reset = 0h]
      7. 5.1.7 CROP_STOP_Y0_CROP_STOP_Y0_P1 Register (Address = 3Ch) [reset = 0h]
      8. 5.1.8 CROP_STOP_Y1_CROP_STOP_Y1_P1 Register (Address = 3Dh) [reset = 0h]
    2. 5.2 Cropping Options
  7. 6 Splitter Mode Pixel Clocks
    1. 6.1 SPLIT_CLK_CTL0_SPLIT_CLK_CTL0_P1 Register (Address = 3Eh) [reset = 81h]
    2. 6.2 SPLIT_CLK_CTL1_SPLIT_CLK_CTL1_P1 Register (Address = 3Fh) [reset = 2h]
  8. 7 Programming Example
  9. 8 Summary
  10. 9 References
  11. 10Handling Interrupts With the DS90Ux941AS-Q1
    1. 10.1 Interrupt Control and Status (INTB and REM_INTB Pin)
    2. 10.2 Handling Interrupts in Splitter Mode Using Remote Interrupt Pin (REM_INTB)
    3. 10.3 REM_INTB_CTRL Register (Address = 30h) [reset = 0h]
  12. 11High-Speed GPIO Operation in Splitter Mode
    1. 11.1 Introduction
    2. 11.2 High-Speed Control Configuration
      1. 11.2.1 DES_CAP1 Registers (Address = 20h)
      2. 11.2.2 DES_CAP2 Registers (Address = 21h)
    3. 11.3 Back Channel Frequency Configuration
    4. 11.4 Splitter Mode GPIO
    5. 11.5 GPIO_0_Config Register (Address = Dh) [reset = 20h]
    6. 11.6 GPIO_1_and_GPIO_2_Config Register (Address = Eh) [reset = 0h]
    7. 11.7 GPIO_3_Config Register (Address = Fh) [reset = 0h]
  13.   Revision History

10.1 Interrupt Control and Status (INTB and REM_INTB Pin)

The HDCP Transmitter can generate an interrupt signal to the attached controller through the INTB pin. This method allows the controller to process some portion of the authentication flow, or to indicate errors in the link status or authentication. The INTB pin is an open-drain, active-low signal that may be shared with other interrupt sources. The HDCP Interrupt Control Register (HDCP_ICR, address 0xC6) enables the various interrupt conditions, while the HDCP Interrupt Status Register (HDCP_ISR, address 0xC7) is used to monitor the interrupt conditions. Bit 0 of the HDCP_ICR is the global interrupt enable that must be set along with at least one other interrupt enable to generate an interrupt on the active low INTB pin.

Upon an interrupt detection, the controller must read the HDCP_ISR register to determine the interrupt condition. Bit 0 of the HDCP_ISR indicates whether or not an interrupt occurred, and the individual status bits indicate which conditions were triggered. The read of the HDCP_ISR also clears the interrupt, which releases the INTB pin. If desired, the controller may then read the HDCP_STS register to determine the current device status. For details on the available interrupt conditions, see the HDCP_ICR and HDCP_ISR register definitions in the data sheet.

The Receiver interrupt—which is bit 5 of HDCP_ICR and HDCP_ISR registers—is a special case. This interrupt is used to propagate an external interrupt from the HDCP Receiver INTB_IN pin to the HDCP Transmitter interrupt pin (INTB). The interrupt is active low and is handled similarly to other interrupt conditions. When the controller detects a falling edge of the interrupt signal, the HDCP Transmitter latches on the interrupt condition, sets the IS_RX_INT bit in the HDCP_ISR register, and asserts the INTB pin low. To clear the interrupt signal, the controller must read the HDCP_ISR to release the INTB and clear the HDCP_ISR. The controller may then check the HDCP_STS:RX_INT bit to determine the current status of the HDCP Receiver's INTB_IN pin. The INTB pin remains deasserted until the next falling edge of the INTB_IN signal. Figure 10-1 shows a typical diagram for the Receiver interrupt propagation.

GUID-0C1A198E-06AF-4F37-B6E7-A09B9B3E7773-low.gifFigure 10-1 Receiver Interrupt Propagation Block Diagram

The sequence for handling the Receiver Interrupt is as follows:

  1. INTB_IN is pulled low by a downstream device.
  2. HDCP Transmitter pulls INTB low.
  3. Controller detects the INTB low and reads the HDCP_ISR register to determine the interrupt source. This clears the interrupt at HDCP Transmitter, which releases the INTB.
  4. The controller typically accesses the remote interrupt source to process the downstream interrupt, which clears the interrupt condition driving INTB_IN.
  5. System is ready to capture another interrupt condition.