SNLA308A April   2019  – October 2020 DS90UB941AS-Q1 , DS90UH941AS-Q1

 

  1.   Trademarks
  2. 1 Introduction
  3. 2 Superframe Requirements
    1. 2.1 Left/Right 3D Format
    2. 2.2 Alternate Line 3D Format
    3. 2.3 Alternate Pixel 3D Format
  4. 3 Video Processing Status Monitoring
    1. 3.1 VIDEO_3D_STS Register (Address = 58h) [reset = 0h]
  5. 4 Superframe Splitting
  6. 5 Frame Cropping
    1. 5.1 Cropping Control Registers
      1. 5.1.1 CROP_START_X0_CROP_START_X0_P1 Register (Address = 36h) [reset = 0h]
      2. 5.1.2 CROP_START_X1_CROP_START_X1_P1 Register (Address = 37h) [reset = 0h]
      3. 5.1.3 CROP_STOP_X0_CROP_STOP_X0_P1 Register (Address = 38h) [reset = 0h]
      4. 5.1.4 CROP_STOP_X1_CROP_STOP_X1_P1 Register (Address = 39h) [reset = 0h]
      5. 5.1.5 CROP_START_Y0_CROP_START_Y0_P1 Register (Address = 3Ah) [reset = 0h]
      6. 5.1.6 CROP_START_Y1_CROP_START_Y1_P1 Register (Address = 3Bh) [reset = 0h]
      7. 5.1.7 CROP_STOP_Y0_CROP_STOP_Y0_P1 Register (Address = 3Ch) [reset = 0h]
      8. 5.1.8 CROP_STOP_Y1_CROP_STOP_Y1_P1 Register (Address = 3Dh) [reset = 0h]
    2. 5.2 Cropping Options
  7. 6 Splitter Mode Pixel Clocks
    1. 6.1 SPLIT_CLK_CTL0_SPLIT_CLK_CTL0_P1 Register (Address = 3Eh) [reset = 81h]
    2. 6.2 SPLIT_CLK_CTL1_SPLIT_CLK_CTL1_P1 Register (Address = 3Fh) [reset = 2h]
  8. 7 Programming Example
  9. 8 Summary
  10. 9 References
  11. 10Handling Interrupts With the DS90Ux941AS-Q1
    1. 10.1 Interrupt Control and Status (INTB and REM_INTB Pin)
    2. 10.2 Handling Interrupts in Splitter Mode Using Remote Interrupt Pin (REM_INTB)
    3. 10.3 REM_INTB_CTRL Register (Address = 30h) [reset = 0h]
  12. 11High-Speed GPIO Operation in Splitter Mode
    1. 11.1 Introduction
    2. 11.2 High-Speed Control Configuration
      1. 11.2.1 DES_CAP1 Registers (Address = 20h)
      2. 11.2.2 DES_CAP2 Registers (Address = 21h)
    3. 11.3 Back Channel Frequency Configuration
    4. 11.4 Splitter Mode GPIO
    5. 11.5 GPIO_0_Config Register (Address = Dh) [reset = 20h]
    6. 11.6 GPIO_1_and_GPIO_2_Config Register (Address = Eh) [reset = 0h]
    7. 11.7 GPIO_3_Config Register (Address = Fh) [reset = 0h]
  13.   Revision History

7 Programming Example

The example code configures the devices for splitting a 2560x720 (2x1280x720, 60 fps, 100-MHz PCLK) superframe with Left/Right 3D from a 4-Lane DSI source to two remote displays with standard 720p and 480p resolutions. The 720p display is assumed to be connected to FPD-Link Port 0, while the 480p display is assumed to be connected to FPD-Link Port 1. The example code also configures the device for cropping the Port1 video after the splitting and before forwarding the data to the 720p display.


WriteI2C (0x01,0x08)    //Disable DSI
WriteI2C (0x1E,0x01)    //Select FPD-Link III Port 0
WriteI2C (0x4F,0x8C)    //Set DSI_CONTINUOUS_CLOCK, 4 lanes, DSI Port 0
WriteI2C (0x5B,0x07)    //Force Splitter mode
WriteI2C (0x56,0x80)    //Enable Left/Right 3D processing to allow superframe splitting
WriteI2C (0x32,0x00)    //Set the line size to 1280(LSB)
WriteI2C (0x33,0x05)    //Set the line size to 1280 (MSB)
//Crop Port0 720p image
WriteI2C (0x1E,0x01)    //Select FPD-Link III Port 1
WriteI2C (0x36,0x00)    //Set crop start X position to 0 (LSB)
WriteI2C (0x37,0x80)    //Set crop start X position to 0 (MSB) and enable cropping
WriteI2C (0x38,0xFF)    //Set crop stop X position to 1279 (LSB)
WriteI2C (0x39,0x04)    //Set crop stop X position to 1279 (MSB)
WriteI2C (0x3A,0x00)    //Set crop start Y position to 0 (LSB)
WriteI2C (0x3B,0x00)    //Set crop start Y position to 0 (MSB)
WriteI2C (0x3C,0xCF)    //Set crop stop Y position to 719 (LSB)
WriteI2C (0x3D,0x02)    //Set crop stop Y position to 719 (MSB)
//Crop Port1 480p image
WriteI2C (0x1E,0x02)    //Select FPD-Link III Port 1
WriteI2C (0x36,0x00)    //Set crop start X position to 0 (LSB)
WriteI2C (0x37,0x80)    //Set crop start X position to 0 (MSB) and enable cropping
WriteI2C (0x38,0x7F)    //Set crop stop X position to 639 (LSB)
WriteI2C (0x39,0x02)    //Set crop stop X position to 639 (MSB)
WriteI2C (0x3A,0x00)    //Set crop start Y position to 0 (LSB)
WriteI2C (0x3B,0x00)    //Set crop start Y position to 0 (MSB)
WriteI2C (0x3C,0xDF)    //Set crop stop Y position to 479 (LSB)
WriteI2C (0x3D,0x01)    //Set crop stop Y position to 479 (MSB)
//Program TSKIP_CNT DSI parameter on DSI Port0
WriteI2C (0x40,0x04)    //Select DSI Port 0 digital registers
WriteI2C (0x41,0x05)    //Select DPHY_SKIP_TIMING register
WriteI2C (0x42,0x1E)    //Write TSKIP_CNT value for 300 MHz DSI clock frequency
WriteI2C (0x01,0x00)    //Enable DSI