SNLA308A April 2019 – October 2020 DS90UB941AS-Q1 , DS90UH941AS-Q1
SPLIT_CLK_CTL1_SPLIT_CLK_CTL1_P1 is described in Table 6-2.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-0 | SPLIT_CLK_DIV_N_SPLI T_CLK_DV_N_P1 | R/W | 2h | Splitter Mode Clock Control Register 1. This controls the selected FPD-Link III port. Splitter mode clock divider N value. This register controls the N setting for the M/N divider used to generate the splitter mode pixel clock from the selected input clock. The default settings for M/N provide a half clock frequency normally required for splitting symmetric video. These values are ignored if Splitter mode is disabled. This controls the selected FPD-Link III port. |