SNLA308A April   2019  – October 2020 DS90UB941AS-Q1 , DS90UH941AS-Q1

 

  1.   Trademarks
  2. 1 Introduction
  3. 2 Superframe Requirements
    1. 2.1 Left/Right 3D Format
    2. 2.2 Alternate Line 3D Format
    3. 2.3 Alternate Pixel 3D Format
  4. 3 Video Processing Status Monitoring
    1. 3.1 VIDEO_3D_STS Register (Address = 58h) [reset = 0h]
  5. 4 Superframe Splitting
  6. 5 Frame Cropping
    1. 5.1 Cropping Control Registers
      1. 5.1.1 CROP_START_X0_CROP_START_X0_P1 Register (Address = 36h) [reset = 0h]
      2. 5.1.2 CROP_START_X1_CROP_START_X1_P1 Register (Address = 37h) [reset = 0h]
      3. 5.1.3 CROP_STOP_X0_CROP_STOP_X0_P1 Register (Address = 38h) [reset = 0h]
      4. 5.1.4 CROP_STOP_X1_CROP_STOP_X1_P1 Register (Address = 39h) [reset = 0h]
      5. 5.1.5 CROP_START_Y0_CROP_START_Y0_P1 Register (Address = 3Ah) [reset = 0h]
      6. 5.1.6 CROP_START_Y1_CROP_START_Y1_P1 Register (Address = 3Bh) [reset = 0h]
      7. 5.1.7 CROP_STOP_Y0_CROP_STOP_Y0_P1 Register (Address = 3Ch) [reset = 0h]
      8. 5.1.8 CROP_STOP_Y1_CROP_STOP_Y1_P1 Register (Address = 3Dh) [reset = 0h]
    2. 5.2 Cropping Options
  7. 6 Splitter Mode Pixel Clocks
    1. 6.1 SPLIT_CLK_CTL0_SPLIT_CLK_CTL0_P1 Register (Address = 3Eh) [reset = 81h]
    2. 6.2 SPLIT_CLK_CTL1_SPLIT_CLK_CTL1_P1 Register (Address = 3Fh) [reset = 2h]
  8. 7 Programming Example
  9. 8 Summary
  10. 9 References
  11. 10Handling Interrupts With the DS90Ux941AS-Q1
    1. 10.1 Interrupt Control and Status (INTB and REM_INTB Pin)
    2. 10.2 Handling Interrupts in Splitter Mode Using Remote Interrupt Pin (REM_INTB)
    3. 10.3 REM_INTB_CTRL Register (Address = 30h) [reset = 0h]
  12. 11High-Speed GPIO Operation in Splitter Mode
    1. 11.1 Introduction
    2. 11.2 High-Speed Control Configuration
      1. 11.2.1 DES_CAP1 Registers (Address = 20h)
      2. 11.2.2 DES_CAP2 Registers (Address = 21h)
    3. 11.3 Back Channel Frequency Configuration
    4. 11.4 Splitter Mode GPIO
    5. 11.5 GPIO_0_Config Register (Address = Dh) [reset = 20h]
    6. 11.6 GPIO_1_and_GPIO_2_Config Register (Address = Eh) [reset = 0h]
    7. 11.7 GPIO_3_Config Register (Address = Fh) [reset = 0h]
  13.   Revision History

2.2 Alternate Line 3D Format

The DS90Ux941AS-Q1 can format a superframe as a dual-image with alternating lines consistent with the Alternate Line 3D format specified in the HDMI 1.4b specification. The DS90Ux941AS-Q1 can be programmed to reformat the alternate line formatted video into a single image with alternating pixels for superframe splitting. The resultant superframe has half the number of video lines that are twice the length. This superframe can be split by the DS90Ux941AS-Q1 at the FPD-Link III output and send the new frames to two independent deserializers.

The following are requirements for proper operation:

  • Images must have identical video format (lines, pixels, blanking intervals)
  • Pixel clock used must be twice the frequency as required for sending a single image
  • Vertical blanking components (front porch, sync period, back porch) must be twice the number of video line periods as required for a single image.
  • Horizontal blanking periods must be the same number of pixels as required for a single image. Note that the total time spent on horizontal blanking in the dual image is twice that of the time spent in the single image, as the horizontal blanking happens for two times the number of lines in a single image.
  • The maximum line size allowed is 4095 pixels (24-bit).
GUID-040B6EB7-868E-4E6B-9B0D-1DDB6F8D18C5-low.pngFigure 2-2 HDMI 1.4b Alternate Line 3D Format

The designer can set the ALT_LINES_3D register bit in the BRIDGE_CTL register (register 0x4F[4]) to enable the alternate line mode.

Alternate Line video processing status can be monitored in the VIDEO_3D_STS register (register 0x58).