SNLA356 September   2020 DS90UB941AS-Q1 , DS90UH941AS-Q1

 

  1.   Abstract
  2.   Trademarks
  3. 1Introduction
  4. 2MIPI DSI Source Requirements
    1. 2.1 Supported DSI Modes
    2. 2.2 Clocking Rates and Clock Type
    3. 2.3 Blanking or Low Power Modes (BLLP)
    4. 2.4 DSI Packet Timing
      1. 2.4.1 Non-Burst Mode With Sync Pulses
      2. 2.4.2 Non-Burst Mode With Sync Events
      3. 2.4.3 Burst Mode
  5. 3Bring-Up and Debug Flow
  6. 4Example Bringup Scenarios
    1. 4.1 Discontinuous Clock
    2. 4.2 Missing Periodic Low Power Transitions
    3. 4.3 Incorrect DSI Packet Timing
    4. 4.4 THS-SKIP Configuration
    5. 4.5 End of Transmission Packets (EoTp)
    6. 4.6 Configuration of Sync Width for Event Mode/Burst Mode
  7. 5Summary
  8. 6References

4.4 THS-SKIP Configuration

The MIPI D-PHY v1.2 receiver specification requires the sink device to ignore activity on the DSI data lanes at the end of high speed packet transmission prior to re-entering the low power state (LP-11) in order to mask transition effects during the End of Transmission (EoT) sequence. If the THS-SKIP timing parameter is mis-configured, it may result in data errors in the DSI video stream.

GUID-78037C7F-E4A3-48AA-9B14-9B10ABC9D555-low.gif Figure 4-6 High-Speed Data Transmission in Bursts

Symptoms:

  • Random/intermittent pixel errors
  • DSI error flags in the DS90UB941AS-Q1 registers
  • Jittering or flickering display

Resolution:

DS90UB941AS-Q1 requires user configuration of the tHS-SKIP timing parameter based on the DSI clock speed applied. The TSKIP_CNT (dec) value is defined in Equation 14, where fDSI is the DSI clock frequency in GHz.

Equation 14. TSKIP_CNT = Round(65*fDSI-5)

This value must get loaded into DS90UB941AS-Q1 register 0x05[6:1] (in hex) prior to enabling the DSI receiver.

Note: The TSKIP_CNT register field is bit shifted left by one bit in the register field.

To program TSKIP_CNT, use the following programming steps via I2C:

  1. Write 0x40 = 0x04 for DSI Port 0 or 0x40 = 0x08 for DSI Port 1
  2. Write 0x41 = 0x05.
  3. Write 0x42 = hex(TSKIP_CNT<<1) from Equation 14.

The DS90Ux941AS-Q1 Superframe Design Calculator tool is available in the DS90UB941AS-Q1 product folder, which also includes calculations for TSKIP_CNT.