SNLA356 September   2020 DS90UB941AS-Q1 , DS90UH941AS-Q1

 

  1.   Abstract
  2.   Trademarks
  3. 1Introduction
  4. 2MIPI DSI Source Requirements
    1. 2.1 Supported DSI Modes
    2. 2.2 Clocking Rates and Clock Type
    3. 2.3 Blanking or Low Power Modes (BLLP)
    4. 2.4 DSI Packet Timing
      1. 2.4.1 Non-Burst Mode With Sync Pulses
      2. 2.4.2 Non-Burst Mode With Sync Events
      3. 2.4.3 Burst Mode
  5. 3Bring-Up and Debug Flow
  6. 4Example Bringup Scenarios
    1. 4.1 Discontinuous Clock
    2. 4.2 Missing Periodic Low Power Transitions
    3. 4.3 Incorrect DSI Packet Timing
    4. 4.4 THS-SKIP Configuration
    5. 4.5 End of Transmission Packets (EoTp)
    6. 4.6 Configuration of Sync Width for Event Mode/Burst Mode
  7. 5Summary
  8. 6References

2.2 Clocking Rates and Clock Type

DS90UB941AS-Q1 supports 25-105MHz PCLK rate over single FPD-Link, or 50-210 MHz PCLK rate over dual FPD-Link. For the MIPI DSI interface, DS90UB941AS-Q1 can support up to 1.5Gbps/lane data rate with up to 4 data lanes. Since MIPI DSI utilizes a DDR (Double Data Rate) clock, the DSI clock speed is typically expressed in MHz where the clock speed is 1/2 the per-lane data rate in Mbps. For example, with a DSI lane speed of 400 Mbps/lane, the MIPI D-PHY clock rate will be 200 MHz. The supported DSI clock rate range for DS90UB941AS-Q1 is 75 MHz-750 MHz.

DS90UB941AS-Q1 supports both continuous and non-continuous clock modes, but care must be taken to select the correct clocking configuration based on the DSI clock type.

Since the supported data formats for DS90UB941AS-Q1 all use a 3-bytes per pixel format, the conversion between DSI clock rate and the video PCLK can be described with a single formula:

Equation 1. fPCLK = (fDSI*NLanes)/12

DS90UB941AS-Q1 supports three different clocking configurations to set the FPD-Link PCLK rate for the serializer output.

  • DSI Reference Clock Mode
  • External Reference Clock Mode
  • Internal Reference Clock Mode (typically used for debug purposes only)

DSI Reference Clock Mode is the most straightforward and commonly used configuration for the serializer. In this mode, the serializer will use the incoming video PCLK derived from Equation 1 as the output PCLK to set the output PCLK speed for the serializer. This configuration eliminates the need for any external clock sources at the serializer, aside from the MIPI D-PHY clock from the video source. In this mode, the DSI clock source must meet the stability requirements of the MIPI D-PHY CTS, and the DSI clock must be continuous.

External Reference Clock Mode utilizes an external clock source connected via the REFCLK0 or REFCLK1 pins to source the output PCLK rate from the serializer. In External Reference Clock mode it is recommended that the REFCLK frequency is matched to the DSI PCLK frequency from Equation 1 unless the DSI source utilizes Burst Mode. This will ensure that the incoming video rate is equal to the outgoing video rate. Although it is possible to apply different clock rates between REFCLK and DSI clock in this mode, the implications for such a configuration are outside the scope of this document. In External Reference Clock Mode, the DSI clock may be either continuous or non-continuous.

Internal Reference Clock Mode utilizes an internal oscillator clock inside DS90UB941AS-Q1 to generate the output video PCLK. This mode is typically utilized for debug purposes, as the stability requirements of the internal oscillator clock are not guaranteed over the entire operating range for voltage and temperature of the device. In Internal Reference Clock mode, the DSI clock may be either continuous or non-continuous.

Note that regardless of operating mode, both the minimum/maximum DSI clock rate and the minimum/maximum PCLK rate for the DS90UB941AS-Q1 must be observed at all times. For example, with fDSI = 75 MHz, 2 DSI data lanes, and DSI Reference Clock Mode, the output video PCLK rate would be 12.5 MHz. However DS90UB941AS-Q1 has a minimum PCLK rate of 25 MHz per FPD-Link channel, so this configuration would not be supported. Likewise, with fDSI = 750 MHz, 4 DSI data lanes, and DSI reference clock mode, the output video PCLK rate would be 250 MHz, which is greater than the maximum support dual FPD-Link PCLK of 210MHz.