SNLA356 September   2020 DS90UB941AS-Q1 , DS90UH941AS-Q1

 

  1.   Abstract
  2.   Trademarks
  3. 1Introduction
  4. 2MIPI DSI Source Requirements
    1. 2.1 Supported DSI Modes
    2. 2.2 Clocking Rates and Clock Type
    3. 2.3 Blanking or Low Power Modes (BLLP)
    4. 2.4 DSI Packet Timing
      1. 2.4.1 Non-Burst Mode With Sync Pulses
      2. 2.4.2 Non-Burst Mode With Sync Events
      3. 2.4.3 Burst Mode
  5. 3Bring-Up and Debug Flow
  6. 4Example Bringup Scenarios
    1. 4.1 Discontinuous Clock
    2. 4.2 Missing Periodic Low Power Transitions
    3. 4.3 Incorrect DSI Packet Timing
    4. 4.4 THS-SKIP Configuration
    5. 4.5 End of Transmission Packets (EoTp)
    6. 4.6 Configuration of Sync Width for Event Mode/Burst Mode
  7. 5Summary
  8. 6References

2.4.2 Non-Burst Mode With Sync Events

  • The DSI transmitter must convey accurate DPI-type timing for HSS, and VSS packets as well as the pixel transmission rate for each active line to match the desired video timing.
  • Since Event Mode does not utilize HSE and VSE packets to define the falling edge of the HSYNC/VSYNC signals, the serializer must be programmed to generate the desired sync widths with the DSI_HSW_CFG and DSI_VSW_CFG registers.
  • The timing of the rising edge of each sync signal is defined by the received timing of the HSS/VSS DSI short packets (which also defines the horizontal and vertical back porch value for the video).
  • The output pixel rate can be defined by the DSI clock rate in continuous clock mode or by the REFCLK source applied to the DS90UB941AS-Q1.
GUID-20200818-CA0I-HXMM-V2NP-13NC5FZQST4D-low.gif Figure 2-2 Non-Burst Mode with Sync Events Packet Structure.