SNLA364C March 2021 – June 2022 DP83TD510E
To configure the TDR circuitry within the PHY, the following registers must be set:
begin
001F 8000
0200 0000
0834 4000
0301 2403
0303 043E
030E 2520
001F 4000
end
Start TDR manually:
begin
//Soft Reset
001F 4000
//Start TDR measurement
001E 8000
end
Check the completion status and results of TDR measurement:
begin
//Soft Reset
001F 4000
// Error Checking
001E //Observe bits [1:0] for completion status, bit [0] must be 1b for TDR status to be valid
//Read TDR result
030C //Observe bits [11:10] for fault detection and [9:0] for fault location
end
The location of the fault is measured in meters and can be found by converting bits 0x030C[9:0] to decimal format.