SNLA415 August   2022 DS160PT801

 

  1.   Abstract
  2.   Trademarks
  3. 1Introduction
  4. 2History
  5. 3Components of PCIe Communication
    1. 3.1 Root Complex
    2. 3.2 Repeater
    3. 3.3 Endpoints
  6. 4Signaling
    1. 4.1 PERST
    2. 4.2 WAKE and CLKREQ
    3. 4.3 REFCLK
  7. 5Link Training
    1. 5.1 Receiver Detect (Rx Detect)
    2. 5.2 Polling
    3. 5.3 Configuration
  8. 6Link Equalization
    1. 6.1 Phase 0 and 1
    2. 6.2 Phase 2 and 3
  9. 7Summary
  10. 8References

6.1 Phase 0 and 1

Phase 0 is the first phase of link equalization. This phase starts when the downstream port sends desired transmitter preset values for each lane to the upstream device. Shortly after receiving the downstream port's request, the upstream port increases the data rate of the link to Gen 3 data rate and begins transmitting training sequences back to the downstream port using the desired presets. Link equalization moves to phase 1 once the connection with Gen 3 is achieved. Figure 6-2 shows the phase 0 of link equalization from Gen 1 to Gen 3 connection with red arrows of each lane pointing the downstream device to represent the upstream device transmitting desired preset values. The link's data rate increases to the data rate of PCIe Gen 3.

GUID-20220805-SS0I-VMG0-GJ1K-T4C99N8MGZ6K-low.png Figure 6-2 Link Equalization Phase 0 and 1

In phase 1, identical training sequences are sent repeatedly to ensure the correct presets are received, despite the possibility of poor link quality. This is done in order to optimize the link enough to be able to exchange training sequences and complete the remaining link equalization phases for fine tuning. Link equalization moves to phase 2 when the link has achieved a link with a bit error rate (BER) of less than 10-4.