SNLA416A September   2022  – February 2024 DS90UB960-Q1 , HD3SS3212-Q1

 

  1.   1
  2.   Abstract
  3. 1Market Need
  4. 2Multiplexing FPD-Link Scheme
  5. 3Multiplexing Execution and Setup
  6. 4Implementation of Switching Protocol
  7. 5Assessing Impact on Signal Integrity
    1. 5.1 Return Loss
    2. 5.2 Insertion Loss
  8. 6Margin Analysis
  9. 7Conclusion
  10. 8References

Return Loss

The return loss for both non-multiplexed and multiplexed channels are within the required limits for stable operation as defined by Texas Instruments FPD-Link SerDes shown in red in Figure 6-4. In this test setup, the hardware used was a variation of the setup shown in Section 2, and this board variation had both CH3 and CH4 connected to a multiplexer. CH1 and CH2 were the non-multiplexed channels in this setup.

GUID-20220831-SS0I-QNXD-6ZRS-ZNRWBSW2CDHQ-low.svgFigure 5-2 Channel Return Loss