SNLA417 January 2023 DP83TC812R-Q1 , DP83TC812S-Q1
Each MDIO frame is 64 bits since the MDIO data follows Clause 22. The data format for clause 22 is in the following list.
Overall, the master configuration sequence in Table 4-1 takes 179 read or write instructions with polling. The MDC was measured to be 3 MHz.
By removing polling, the master configuration time is decreased since polling creates unnecessary read instructions. When removing all unnecessary read instructions, only 90 instructions are needed to configure the PHY as master. Most of these write instructions involve extended registers, which require 4 writes to successfully write to them.
Removing the optional preamble is also beneficial because the preamble is not needed for the read and write transactions. This decreases the size of each MDIO frame to 32 bits.
Δtms_cfg= 90 instructions × 32 bits × (1/3 MHz) = 0.960ms. This is 2.954ms less than the actual time measured.